Travelled to:1 × Germany
1 × India
6 × USA
Collaborated with:L.Eeckhout D.Genbrugge K.D.Bosschere K.D.Bois J.B.Sartor T.Karkhanis J.E.Smith
Talks about:processor (4) smt (4) thread (3) level (3) architectur (2) parallel (2) perform (2) simul (2) multi (2) probabilist (1)
Person: Stijn Eyerman
DBLP: Eyerman:Stijn
Contributed to:
2014
20132010
2010200920072006
2006Wrote 8 papers:
- ASPLOS-2014-EyermanE #concurrent #flexibility #manycore #parallel #smt #thread #towards
- The benefit of SMT in the multi-core era: flexibility towards degrees of thread-level parallelism (SE, LE), pp. 591–606.
- OOPSLA-2013-BoisSEE #concurrent #graph #multi #scalability #thread #visualisation
- Bottle graphs: visualizing scalability bottlenecks in multi-threaded applications (KDB, JBS, SE, LE), pp. 355–372.
- ASPLOS-2010-EyermanE #modelling #probability #scheduling #smt
- Probabilistic job symbiosis modeling for SMT processor scheduling (SE, LE), pp. 91–102.
- HPCA-2010-GenbruggeEE #abstraction #architecture #simulation
- Interval simulation: Raising the level of abstraction in architectural simulation (DG, SE, LE), pp. 1–12.
- ASPLOS-2009-EyermanE #smt #thread
- Per-thread cycle accounting in SMT processors (SE, LE), pp. 133–144.
- HPCA-2007-EyermanE #parallel #policy #smt
- A Memory-Level Parallelism Aware Fetch Policy for SMT Processors (SE, LE), pp. 240–249.
- ASPLOS-2006-EyermanEKS #architecture #component #performance
- A performance counter architecture for computing accurate CPI components (SE, LE, TK, JES), pp. 175–184.
- DATE-2006-EyermanEB #design #embedded #performance
- Efficient design space exploration of high performance embedded out-of-order processors (SE, LE, KDB), pp. 351–356.