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Travelled to:
3 × USA
Collaborated with:
T.Fujimoto T.Chiba T.Inufushi N.Okuda I.Nishioka S.Kimura S.Kimura
Talks about:
system (2) vlsi (2) placement (1) algorithm (1) hierarch (1) polycel (1) layout (1) design (1) verif (1) sharp (1)

Person: Takashi Kambe

DBLP DBLP: Kambe:Takashi

Contributed to:

DAC 19961996
DAC 19821982
DAC 19811981

Wrote 3 papers:

DAC-1996-FujimotoK #design #verification
VLSI Design and System Level Verification for the Mini-Disc (TF, TK), pp. 491–496.
DAC-1982-KambeCKION #algorithm #evaluation
A placement algorithm for polycell LSI and ITS evaluation (TK, TC, SK, TI, NO, IN), pp. 655–662.
DAC-1981-ChibaOKNIK #layout #named
SHARPS: A hierarchical layout system for VLSI (TC, NO, TK, IN, TI, SK), pp. 820–827.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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