Travelled to:3 × USA
Collaborated with:T.Kambe T.Chiba T.Inufushi I.Nishioka I.Shirakawa T.Harada S.Tani H.Ozaki S.Kimura S.Kimura
Talks about:system (2) layout (2) lsi (2) placement (1) algorithm (1) hierarch (1) portion (1) polycel (1) random (1) sharp (1)
Person: Noboru Okuda
DBLP: Okuda:Noboru
Contributed to:
198219811980Wrote 3 papers:
- DAC-1982-KambeCKION #algorithm #evaluation
- A placement algorithm for polycell LSI and ITS evaluation (TK, TC, SK, TI, NO, IN), pp. 655–662.
- DAC-1981-ChibaOKNIK #layout #named
- SHARPS: A hierarchical layout system for VLSI (TC, NO, TK, IN, TI, SK), pp. 820–827.
- DAC-1980-ShirakawaOHTO #layout #logic #random
- A layout system for the random logic portion of MOS LSI (IS, NO, TH, ST, HO), pp. 92–99.