Travelled to:1 × France
1 × Germany
3 × USA
Collaborated with:J.Baumgartner A.Kuehlmann M.K.Ganai H.Mony R.Kanzelman C.Jacobi K.Weber U.Krautz A.Arunagiri S.Kumar S.Pujar T.Babinsky S.Bergman G.Bobok W.Kowalski S.Koyfman S.Moran Z.Nevo A.Orni W.Roesner G.Shurek V.Vuyyuru
Talks about:verif (3) automat (2) multipli (1) industri (1) without (1) suspect (1) exploit (1) circuit (1) boolean (1) redund (1)
Person: Viresh Paruthi
DBLP: Paruthi:Viresh
Contributed to:
2015
2014200520052001Wrote 5 papers:
- DATE-2015-BergmanBKKMNOPR #experience #industrial #verification
- Designer-level verification: an industrial experience story (SB, GB, WK, SK, SM, ZN, AO, VP, WR, GS, VV), pp. 410–411.
- DAC-2014-KrautzPAKPB #automation #float #verification
- Automatic Verification of Floating Point Units (UK, VP, AA, SK, SP, TB), p. 6.
- DAC-2005-MonyBPK #proving
- Exploiting suspected redundancy without proving it (HM, JB, VP, RK), pp. 463–466.
- DATE-2005-JacobiWPB #automation #multi #verification
- Automatic Formal Verification of Fused-Multiply-Add FPUs (CJ, KW, VP, JB), pp. 1298–1303.
- DAC-2001-KuehlmannGP #reasoning
- Circuit-based Boolean Reasoning (AK, MKG, VP), pp. 232–237.