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Travelled to:
1 × France
Collaborated with:
H.R.Gonçalves X.Li M.V.Correia J.M.C.Jr. K.M.Butler
Talks about:
algorithm (1) spatial (1) circuit (1) variat (1) reduct (1) effici (1) analog (1) model (1) test (1) fast (1)

Person: Vitor Tavares

DBLP DBLP: Tavares:Vitor

Contributed to:

DATE 20152015

Wrote 1 papers:

DATE-2015-GoncalvesLCTCB #algorithm #modelling #performance #reduction
A fast spatial variation modeling algorithm for efficient test cost reduction of analog/RF circuits (HRG, XL, MVC, VT, JMCJ, KMB), pp. 1042–1047.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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