Travelled to:3 × USA
Collaborated with:S.Prasitjutrakul S.T.Healey J.F.P.Luhukay I.Suwa Y.C.Hsu Y.Pan
Talks about:system (2) path (2) cell (2) placement (1) floorplan (1) constrain (1) synthesi (1) mathemat (1) approach (1) abstract (1)
Person: William J. Kubitz
DBLP: Kubitz:William_J=
Contributed to:
1989198719821981Wrote 5 papers:
- DAC-1989-PrasitjutrakulK #approach #programming
- Path-Delay Constrained Floorplanning: A Mathematical Programming Approach for Initial Placement (SP, WJK), pp. 364–369.
- DAC-1987-HealeyK #generative #logic #network
- Abstract Routing of Logic Networks for Custom Module Generation (STH, WJK), pp. 230–236.
- DAC-1987-HsuPK
- A Path Selection Global Router (YCH, YP, WJK), pp. 641–644.
- DAC-1982-LuhukayK #layout #synthesis
- A layout synthesis system for NMOS gate-cells (JFPL, WJK), pp. 307–314.
- DAC-1981-SuwaK
- A computer-aided-design system for segmented-folded PLA macro-cells (IS, WJK), pp. 398–405.