Travelled to:1 × China
1 × France
2 × Germany
3 × USA
Collaborated with:T.Kim T.Krishna L.Peh S.Yoo K.Choi S.Eo J.Um S.Hong B.Min C.O.Chen S.Jeong S.Hong Y.Kim J.Kong
Talks about:chip (3) voltag (2) memori (2) base (2) no (2) subsystem (1) processor (1) techniqu (1) systemat (1) platform (1)
Person: Woo-Cheol Kwon
DBLP: Kwon:Woo=Cheol
Contributed to:
2014
2013
2009
2008200820062003Wrote 7 papers:
- ASPLOS-2014-KwonKP #multi
- Locality-oblivious cache organization leveraging single-cycle multi-hop NoCs (WCK, TK, LSP), pp. 715–728.
- HPCA-2013-KrishnaCKP #latency #using
- Breaking the on-chip latency barrier using SMART (TK, CHOC, WCK, LSP), pp. 378–389.
- DATE-2009-KwonYUJ #performance #problem
- In-network reorder buffer to improve overall NoC performance while resolving the in-order requirement problem (WCK, SY, JU, SWJ), pp. 1058–1063.
- DAC-2008-KwonYHMCE #approach #memory management #parallel
- A practical approach of memory access parallelization to exploit multiple off-chip DDR memories (WCK, SY, SMH, BM, KMC, SKE), pp. 447–452.
- DATE-2008-KwonHYMCE #communication
- An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication (WCK, SMH, SY, BM, KMC, SKE), pp. 1244–1249.
- DATE-2006-UmKHKCKEK #design #modelling #platform
- A systematic IP and bus subsystem modeling for platform-based system design (JU, WCK, SH, YTK, KMC, JTK, SKE, TK), pp. 560–564.
- DAC-2003-KwonK
- Optimal voltage allocation techniques for dynamically variable voltage processors (WCK, TK), pp. 125–130.