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Travelled to:
1 × France
13 × USA
2 × Germany
Collaborated with:
K.Chung Y.Choi J.Um D.Joo C.L.Liu J.Seo C.Liu W.Kwon T.Kim H.Jang J.Kim C.Lyuh K.Park G.Kim J.Kim K.Lim Y.Kim Y.Choi N.Chang P.R.Panda W.Jao S.W.K.Tjiang S.Hong Y.Kim K.Choi J.Kong S.Eo
Talks about:
synthesi (8) memori (7) buffer (6) optim (6) system (5) design (5) power (5) clock (5) techniqu (4) schedul (4)

Person: Taewhan Kim

DBLP DBLP: Kim:Taewhan

Contributed to:

DATE 20142014
DAC 20132013
DAC 20112011
DAC 20102010
DAC 20092009
DAC 20072007
DATE 20062006
DAC 20052005
DAC 20042004
DAC 20032003
DAC 20022002
DAC 20012001
DAC 20002000
DAC 19981998
EDAC-ETC-EUROASIC 19941994
DAC 19931993

Wrote 21 papers:

DATE-2014-ParkKK #design #multi #synthesis
Mixed allocation of adjustable delay buffers combined with buffer sizing in clock tree synthesis of multiple power mode designs (KP, GK, TK), pp. 1–4.
DAC-2013-KimJK #algorithm #problem
An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem (JK, DJ, TK), p. 6.
DAC-2011-JooK #fine-grained #named
WaveMin: a fine-grained clock buffer polarity assignment combined with buffer sizing (DJ, TK), pp. 522–527.
DAC-2010-KimK #3d #design #synthesis #testing
Clock tree synthesis with pre-bond testability for 3D stacked IC designs (TYK, TK), pp. 723–728.
DAC-2009-JangK
Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization (HJ, TK), pp. 794–799.
DAC-2007-LimKK #architecture #communication #distributed #synthesis
Interconnect and Communication Synthesis for Distributed Register-File Microarchitecture (KHL, YK, TK), pp. 765–770.
DATE-2006-UmKHKCKEK #design #modelling #platform
A systematic IP and bus subsystem modeling for platform-based system design (JU, WCK, SH, YTK, KMC, JTK, SKE, TK), pp. 560–564.
DAC-2005-ChoiCK #embedded #power management
DC-DC converter-aware power management for battery-operated embedded systems (YC, NC, TK), pp. 895–900.
DAC-2005-KimK #array #design #embedded #memory management #optimisation #scheduling
Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design (JK, TK), pp. 105–110.
DAC-2004-LyuhK #energy #memory management #multi #scheduling
Memory access scheduling and binding considering energy minimization in multi-bank memory systems (CGL, TK), pp. 81–86.
DAC-2004-SeoKC #realtime #scheduling
Profile-based optimal intra-task voltage scheduling for hard real-time applications (JS, TK, KSC), pp. 87–92.
DAC-2003-ChoiK #design #embedded #layout #memory management #performance
Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design (YC, TK), pp. 881–886.
DAC-2003-KwonK
Optimal voltage allocation techniques for dynamically variable voltage processors (WCK, TK), pp. 125–130.
DAC-2002-ChoiK #code generation #scheduling
Address assignment combined with scheduling in DSP code generation (YC, TK), pp. 225–230.
DAC-2002-SeoKP #algorithm #memory management #synthesis
An integrated algorithm for memory allocation and assignment in high-level synthesis (JS, TK, PRP), pp. 608–611.
DAC-2002-UmK #synthesis
Layout-aware synthesis of arithmetic circuits (JU, TK), pp. 207–212.
DAC-2001-KimCL #estimation #logic
A Static Estimation Technique of Power Sensitivity in Logic Circuits (TK, KSC, CLL), pp. 215–219.
DAC-2000-UmKL #fine-grained #optimisation #power management #synthesis
A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis (JU, TK, CLL), pp. 98–103.
DAC-1998-KimJT #optimisation #using
Arithmetic Optimization Using Carry-Save-Adders (TK, WJ, SWKT), pp. 433–438.
EDAC-1994-KimCL #refinement #synthesis #testing
A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability (TK, KSC, CLL), pp. 586–590.
DAC-1993-KimL #multi #synthesis
Utilization of Multiport Memories in Data Path Synthesis (TK, CLL), pp. 298–302.

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