BibSLEIGH — Sungjoo

Travelled to:

5 × Germany
6 × France
9 × USA

Collaborated with:

S.Lee A.A.Jerraya K.Choi J.Ahn L.Gauthier G.Nicolescu H.Park W.Kwon D.Kim Y.Kim Y.Paviot K.Choi S.Eo J.Jung J.H.Ahn M.Youssef A.Bouchhima S.Hong Y.Cho A.Baghdadi D.Lyonnard S.Lee J.Yun G.Kim J.Kim J.Yoo J.Kim C.Kyung S.Hong B.Min M.Diaz-Nava E.Park H.Li Y.Choi J.Um S.Jeong E.Park M.Son K.Kim H.Kim D.Kim J.Kim S.Kwon H.Jung A.Sasongko G.Lee N.Zergainoh I.Bacivarov B.Bin T.Kim J.Lee K.Rha J.Chung D.Kim D.H.Woo W.O.Cesário

Talks about:

memori (10) design (8) chip (8) system (7) base (7) perform (5) phase (5) processor (4) softwar (4) hardwar (4)

Person: Sungjoo Yoo

DBLP: Yoo:Sungjoo

Contributed to:

2015

2014

2012

2011

2009

2008

2004

2003

2002

2001

2000

Wrote 33 papers:

DATE-2015-ParkAHYL #big data #energy #gpu #low cost #memory management #performance: Memory fast-forward: a low cost special function unit to enhance energy efficiency in GPU for big data processing (EP, JA, SH, SY, SL), pp. 1341–1346.
DATE-2015-SonLKYL #smarttech: A small non-volatile write buffer to reduce storage writes in smartphones (MS, SL, KK, SY, SL), pp. 713–718.
DAC-2014-AhnYC #hybrid #memory management #power management: Dynamic Power Management of Off-Chip Links for Hybrid Memory Cubes (JA, SY, KC), p. 6.
DATE-2014-KimKKYL #design: Coarse-grained Bubble Razor to exploit the potential of two-phase transparent latch designs (HK, DK, JJK, SY, SL), pp. 1–6.
DATE-2014-ParkYLL #graph #memory management #representation: Accelerating graph computation with racetrack memory and pointer-assisted graph representation (EP, SY, SL, HL), pp. 1–4.
HPCA-2014-AhnYC #architecture #named #predict: DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture (JA, SY, KC), pp. 25–36.
DAC-2012-KimLCKWYL #cpu #gpu #hybrid #in memory #memory management: Hybrid DRAM/PRAM-based main memory for single-chip CPU/GPU (DK, SL, JC, DK, DHW, SY, SL), pp. 888–896.
DAC-2012-KimYL #latency #performance #ram: Write performance improvement by hiding R drift latency in phase-change RAM (YK, SY, SL), pp. 897–906.
DATE-2012-KwonKKYL #case study #in memory #memory management #ram: A case study on the application of real phase-change RAM to main memory subsystem (SK, DK, YK, SY, SL), pp. 264–267.
DATE-2012-YunLY #ram: Bloom filter-based dynamic wear leveling for phase-change RAM (JY, SL, SY), pp. 1513–1518.
DAC-2011-ChoiYLA #behaviour #fault #performance: Matching cache access behavior and bit error pattern for high performance low Vcc L1 cache (YGC, SY, SL, JHA), pp. 978–983.
DAC-2011-KimKY #named #network #power management: FlexiBuffer: reducing leakage power in on-chip network routers (GK, JK, SY), pp. 936–941.
DAC-2011-ParkYL #hybrid #in memory #memory management #power management: Power management of hybrid DRAM/PRAM-based main memory (HP, SY, SL), pp. 59–64.
DATE-2011-KimYLAJ #3d #analysis #embedded #mobile #performance: A quantitative analysis of performance benefits of 3D die stacking on mobile and embedded SoC (DK, SY, SL, JHA, HJ), pp. 1333–1338.
DATE-2011-ParkYL #novel #power management: A novel tag access scheme for low power L2 cache (HP, SY, SL), pp. 655–660.
DAC-2009-YooYC #design #memory management #multi #performance: Multiprocessor System-on-Chip designs with active memory processors for higher memory efficiency (JhY, SY, KC), pp. 806–811.
DATE-2009-KimYK #online #runtime #scalability: Program phase and runtime distribution-aware online DVFS for combined Vdd/Vbb scaling (JK, SY, CMK), pp. 417–422.
DATE-2009-KwonYUJ #performance #problem: In-network reorder buffer to improve overall NoC performance while resolving the in-order requirement problem (WCK, SY, JU, SWJ), pp. 1058–1063.
DAC-2008-KwonYHMCE #approach #memory management #parallel: A practical approach of memory access parallelization to exploit multiple off-chip DDR memories (WCK, SY, SMH, BM, KMC, SKE), pp. 447–452.
DATE-2008-HongYBCEK #bias #runtime #scalability: Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution (SH, SY, BB, KMC, SKE, TK), pp. 242–247.
DATE-2008-KwonHYMCE #communication: An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication (WCK, SMH, SY, BM, KMC, SKE), pp. 1244–1249.
DAC-2004-YoussefYSPJ #case study #debugging #design #interface #video: Debugging HW/SW interface for MPSoC: video encoder system design case study (MWY, SY, AS, YP, AAJ), pp. 908–913.
DATE-v2-2004-YooYBJD #concept #design #multi #using: Multi-Processor SoC Design Methodology Using a Concept of Two-Layer Hardware-Dependent Software (SY, MWY, AB, AAJ, MDN), pp. 1382–1383.
DATE-2003-ChoLYCZ #analysis #communication #design #scheduling: Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design (YC, GL, SY, KC, NEZ), pp. 20132–20137.
DATE-2003-YooBBPJ #abstraction #hardware #modelling #performance #simulation: Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer (SY, IB, AB, YP, AAJ), pp. 10550–10555.
DATE-2003-YooJ #abstraction #hardware: Introduction to Hardware Abstraction Layers for SoC (SY, AAJ), pp. 10336–10337.
DAC-2002-CesarioBGLNPYJD #approach #component #design #manycore: Component-based design approach for multicore SoCs (WOC, AB, LG, DL, GN, YP, SY, AAJ, MDN), pp. 789–794.
DATE-2002-YooNGJ #automation #design #generative #modelling #operating system #performance #simulation: Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design (SY, GN, LG, AAJ), pp. 620–627.
DAC-2001-LyonnardYBJ #architecture #automation #generative #multi: Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip (DL, SY, AB, AAJ), pp. 518–523.
DATE-2001-GauthierYJ #automation #embedded #generative #operating system: Automatic generation and targeting of application specific operating systems and embedded systems software (LG, SY, AAJ), pp. 679–685.
DATE-2001-JungYC #analysis #multi #performance: Performance improvement of multi-processor systems cosimulation based on SW analysis (JJ, SY, KC), pp. 749–753.
DATE-2001-NicolescuYJ #communication #design #refinement: Mixed-level cosimulation for fine gradual refinement of communication in SoC design (GN, SY, AAJ), pp. 754–759.
DATE-2000-YooLJRCC #execution #performance: Fast Hardware-Software Coverification by Optimistic Execution of Real Processor (SY, JeL, JJ, KR, YC, KC), pp. 663–668.