Travelled to:1 × France
3 × Germany
3 × USA
Collaborated with:K.Choi S.Yoo W.Kwon Y.Kim J.Kong S.Hong B.Min S.Hong C.Shin E.Chung B.Bin T.Kim L.Sarno R.Wilson L.Lestringand J.Goodenough G.Stark S.Leef D.Witt J.Um T.Kim F.Bacchini D.Maliniak T.Doherty P.McShane S.A.Pai S.Sundararajan P.Urard T.Kim Y.Kim
Talks about:bus (3) architectur (2) communic (2) exploit (2) system (2) memori (2) design (2) model (2) accur (2) show (2)
Person: Soo-Kwan Eo
DBLP: Eo:Soo=Kwan
Contributed to:
2008
200820072006200520052004Wrote 8 papers:
- DAC-2008-KwonYHMCE #approach #memory management #parallel
- A practical approach of memory access parallelization to exploit multiple off-chip DDR memories (WCK, SY, SMH, BM, KMC, SKE), pp. 447–452.
- DATE-2008-HongYBCEK #bias #runtime #scalability
- Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution (SH, SY, BB, KMC, SKE, TK), pp. 242–247.
- DATE-2008-KwonHYMCE #communication
- An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication (WCK, SMH, SY, BM, KMC, SKE), pp. 1244–1249.
- DAC-2007-SarnoWELGSLW #ll
- IP Exchange: I’ll Show You Mine if You Show Me Yours (LS, RW, SKE, LL, JG, GS, SL, DW), pp. 990–991.
- DATE-2006-UmKHKCKEK #design #modelling #platform
- A systematic IP and bus subsystem modeling for platform-based system design (JU, WCK, SH, YTK, KMC, JTK, SKE, TK), pp. 560–564.
- DAC-2005-BacchiniMDMPSEU #named
- ESL: building the bridge between systems to silicon (FB, DM, TD, PM, SAP, SS, SKE, PU), pp. 69–70.
- DATE-2005-KimKKSCCKE #architecture #modelling #performance #transaction
- Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture (YTK, TK, YK, CS, EYC, KMC, JTK, SKE), pp. 138–139.
- DATE-v1-2004-ShinKCCKE #architecture #design #performance
- Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design (CS, YTK, EYC, KMC, JTK, SKE), pp. 352–357.