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Travelled to:
1 × France
Collaborated with:
P.R.Menon
Talks about:
synthesi (1) circuit (1) verifi (1) level (1) delay (1) two (1)

Person: Wuudiann Ke

DBLP DBLP: Ke:Wuudiann

Contributed to:

EDAC-ETC-EUROASIC 19941994

Wrote 1 papers:

EDAC-1994-KeM #synthesis
Synthesis of Delay-Verifiable Two-Level Circuits (WK, PRM), pp. 297–301.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.