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Travelled to:
3 × USA
Collaborated with:
P.Li W.Dong Y.Zhan Z.Zeng Z.Feng
Talks about:
optim (3) parallel (2) circuit (2) simul (2) power (2) multi (2) transient (1) algorithm (1) tradeoff (1) deliveri (1)

Person: Xiaoji Ye

DBLP DBLP: Ye:Xiaoji

Contributed to:

DAC 20102010
DAC 20082008
DAC 20072007

Wrote 4 papers:

DAC-2010-YeL #modelling #optimisation #parallel #performance #runtime #simulation
Parallel program performance modeling for runtime optimization of multi-algorithm circuit simulation (XY, PL), pp. 561–566.
DAC-2010-ZengYFL #analysis #network #optimisation #power management #trade-off
Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation (ZZ, XY, ZF, PL), pp. 831–836.
DAC-2008-DongLY #manycore #named #parallel #simulation
WavePipe: parallel transient simulation of analog and digital circuits on multi-core shared-memory machines (WD, PL, XY), pp. 238–243.
DAC-2007-YeZL #optimisation #performance #power management #statistics #using
Statistical Leakage Power Minimization Using Fast Equi-Slack Shell Based Optimization (XY, YZ, PL), pp. 853–858.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.