Travelled to:1 × France
1 × USA
Collaborated with:H.Wu R.Tsay Y.Lu F.Yu B.Zeng C.Lee
Talks about:synchron (2) simul (2) time (2) determinist (1) interfac (1) instruct (1) approach (1) section (1) hardwar (1) intrus (1)
Person: Yu-Hung Huang
DBLP: Huang:Yu=Hung
Contributed to:
2013
2012Wrote 2 papers:
- DATE-2013-YuZHWLT #approach #manycore #set #simulation
- A critical-section-level timing synchronization approach for deterministic multi-core instruction set simulations (FWY, BHZ, YHH, HIW, CRL, RST), pp. 643–648.
- DAC-2012-HuangLWT #interface
- A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulation (YHH, YSL, HIW, RST), pp. 127–132.