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Travelled to:
2 × USA
Collaborated with:
S.Chang D.Wang M.Marek-Sadowska C.Lung S.Huang Y.Shi
Talks about:
variabl (1) perform (1) network (1) mechan (1) latenc (1) effici (1) design (1) toler (1) optim (1) fault (1)

Person: Yu-Shih Su

DBLP DBLP: Su:Yu=Shih

Contributed to:

DAC 20112011
DAC 20072007

Wrote 2 papers:

DAC-2011-LungSHSC #3d #fault tolerance #network
Fault-tolerant 3D clock network (CLL, YSS, SHH, YS, SCC), pp. 645–651.
DAC-2007-SuWCM #design #optimisation #performance
An Efficient Mechanism for Performance Optimization of Variable-Latency Designs (YSS, DCW, SCC, MMS), pp. 976–981.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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