BibSLEIGH
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Used together with:
video (3)
mpeg (3)
design (3)
scale (3)
chip (2)

Stem codec$ (all stems)

10 papers:

DATEDATE-2009-ShafiqueBH #approach #design #hardware #parallel #performance #predict #video
A parallel approach for high performance hardware design of intra prediction in H.264/AVC Video Codec (MS, LB, JH), pp. 1434–1439.
DACDAC-2008-DuanZK #design
Forbidden transition free crosstalk avoidance CODEC design (CD, CZ, SPK), pp. 986–991.
DACDAC-2006-HanGCJ #memory management #optimisation #video
Buffer memory optimization for video codec application modeled in Simulink (SIH, XG, SIC, AAJ), pp. 689–694.
DATEDATE-DF-2006-YehWLW #multi #programmable
A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applications (CY, CCW, LCL, JSW), pp. 239–243.
DACDAC-2005-UrardPGMLYG
A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC paper 24.3) (PU, LP, PG, TM, VL, EY, BG), pp. 547–548.
DATEDATE-2005-EeckhautDSCS #scalability #video
A Hardware-Friendly Wavelet Entropy Codec for Scalable Video (HE, HD, BS, MC, DS), pp. 14–19.
DATEDATE-2005-LianHFCC #development #parsing expression grammar
PEG, MPEG-4, and H.264 Codec IP Development (CJL, YWH, HCF, YCC, LGC), pp. 1118–1119.
DATEDATE-2003-IwasakiNNNYONTOIE #multi #scalability
Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level (HI, JN, KN, KN, TY, MO, YN, YT, TO, MI, ME), pp. 20002–20007.
DACDAC-2000-PhelpsKRCH #case study #synthesis
A case study of synthesis for industrial-scale analog IP: redesign of the equalizer/filter frontend for an ADSL CODEC (RP, MK, RAR, LRC, JRH), pp. 1–6.
DACDAC-1998-UsamiIIKTHATK #design #power management #scalability
Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques (KU, MI, TI, MK, MT, MH, HA, TT, TK), pp. 483–488.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.