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Used together with:
base (5)
logic (4)
polar (3)
silicon (3)
devic (3)

Stem nanowir$ (all stems)

16 papers:

CASECASE-2015-YuYS #multi
Motion planning and manipulation of multiple nanowires simultaneouly under electric-fields in fluid suspension (KY, JY, JS), pp. 489–494.
DACDAC-2015-SuC #complexity
Nanowire-aware routing considering high cut mask complexity (YHS, YWC), p. 6.
DATEDATE-2015-MohammadiGM #fault #modelling
Fault modeling in controllable polarity silicon nanowire circuits (HGM, PEG, GDM), pp. 453–458.
III-V semiconductor nanowires for future devices (HS, BMB, KM, PDK, GS, SFK, PM, VS, HR), pp. 1–2.
DATEDATE-2014-WangYSK #encryption #energy #in memory #performance
Energy efficient in-memory AES encryption based on nonvolatile domain-wall nanowire (YW, HY, DS, PK), pp. 1–4.
DATEDATE-2014-WeberTGHKM #challenge #configuration management
Reconfigurable silicon nanowire devices and circuits: Opportunities and challenges (WMW, JT, MG, AH, MK, TM), pp. 1–6.
Electrophoresis-based motion planning and control of a nanowire in fluid suspension (KY, XL, JY, JS), pp. 819–824.
DACDAC-2013-GaillardonMABSLM #towards #using
Towards structured ASICs using polarity-tunable Si nanowire transistors (PEG, MDM, LGA, SB, DS, YL, GDM), p. 4.
Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs (PEG, LGA, SB, MDM, DS, YL, GDM), pp. 625–630.
DACDAC-2012-BobbaMLM #physics #synthesis
Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors (SB, MDM, YL, GDM), pp. 42–47.
CMOS compatible nanowires for biosensing (ES, DAR, AV, NKR, JMC, JP, TMF, MR), pp. 718–722.
CASECASE-2010-RuZSZSHC #automation #metric
Automated four-point probe measurement of nanowires inside a scanning electron microscope (CR, YZ, YS, YZ, XS, DH, IC), pp. 533–538.
DACDAC-2009-JamaaLM #array #multi
Decoding nanowire arrays fabricated with the multi-spacer patterning technique (MHBJ, YL, GDM), pp. 77–82.
DATEDATE-2009-ZhengH #array #logic #programmable #satisfiability
Defect-aware logic mapping for nanowire-based programmable logic arrays via satisfiability (YZ, CH), pp. 1279–1283.
DATEDATE-2008-DongZ #integration #logic #standard #synthesis
Logic Synthesis with Nanowire Crossbar: Reality Check and Standard Cell-based Integration (MD, LZ), pp. 268–271.
DACDAC-2006-RaoOK #architecture #logic
Topology aware mapping of logic functions onto nanowire-based crossbar architectures (WR, AO, RK), pp. 723–726.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.