21 papers:
DAC-2014-ApostolopoulouDES #matrix #scalability #simulation- Selective Inversion of Inductance Matrix for Large-Scale Sparse RLC Simulation (IA, KD, NEE, GIS), p. 6.
DATE-2014-BanagaayaAST #network #order #reduction- Implicit index-aware model order reduction for RLC/RC networks (NB, GA, WHAS, CT), pp. 1–6.
- DATE-2009-TaoL #grid #power management
- Decoupling capacitor planning with analytical delay model on RLC power grid (YT, SKL), pp. 839–844.
- DAC-2007-YanTLM #higher-order #named #reduction
- SBPOR: Second-Order Balanced Truncation for Passive Order Reduction of RLC Circuits (BY, SXDT, PL, BM), pp. 158–161.
- DATE-2006-TanjiWKA #analysis #scalability #using
- Large scale RLC circuit analysis using RLCG-MNA formulation (YT, TW, HK, HA), pp. 45–46.
- DAC-2004-TanjiA #analysis #distributed
- Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effects (YT, HA), pp. 810–813.
- DAC-2003-AgarwalSB #effectiveness
- An effective capacitance based driver output model for on-chip RLC interconnects (KA, DS, DB), pp. 376–381.
- DAC-2002-MaH #constraints #towards
- Towards global routing with RLC crosstalk constraints (JDZM, LH), pp. 669–672.
- DAC-2002-SuBK #framework #reduction
- A factorization-based framework for passivity-preserving model reduction of RLC systems (QS, VB, CKK), pp. 40–45.
- DAC-2002-VenkatesanDM #distributed #physics
- A physical model for the transient response of capacitively loaded distributed rlc interconnects (RV, JAD, JDM), pp. 763–766.
- DATE-2002-ZhengPBK #analysis #modelling #scalability
- Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses (HZ, LTP, MWB, BK), pp. 628–633.
- DAC-2001-BanerjeeM #analysis #distributed #novel #optimisation #performance #using
- Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects (KB, AM), pp. 798–803.
- DAC-2001-LepakLH #constraints
- Simultaneous Shield Insertion and Net Ordering under Explicit RLC Noise Constraint (KML, IL, LH), pp. 199–202.
- DATE-2000-ChangLNXH #modelling #performance
- Clocktree RLC Extraction with Efficient Inductance Modeling (NC, SL, OSN, WX, LH), pp. 522–526.
- DAC-1999-IsmailFN
- Equivalent Elmore Delay for RLC Trees (YII, EGF, JLN), pp. 715–720.
- DAC-1999-Sheehan #equation #named #order #performance #reduction #using
- ENOR: Model Order Reduction of RLC Circuits Using Nodal Equations for Efficient Factorization (BNS), pp. 17–21.
- DATE-1999-Sheehan #reduction #using
- Projective Convolution: RLC Model-Order Reduction Using the Impulse Response (BNS), p. 669–?.
- DAC-1998-LiuPS #modelling #named #order
- ftd: An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect Models (YL, LTP, AJS), pp. 469–472.
- DAC-1997-KernsY #congruence #network #reduction
- Preservation of Passivity During RLC Network Reduction via Split Congruence Transformations (KJK, ATY), pp. 34–39.
- DAC-1993-HaqueC #analysis #design #distributed #reliability
- Analysis and Reliable Design of ECL Circuits with Distributed RLC Interconnections (MH, SC), pp. 697–701.
- DAC-1988-GuraA #simulation
- Improved Methods of Simulating RLC Couple and Uncoupled Transmission Lines Based on the Method of Characteristics (CVG, JAA), pp. 300–305.
