BibSLEIGH — High-Level Synthesis from VHDL with Exact Timing Constraints

A. Stoll, Peter Duzy
High-Level Synthesis from VHDL with Exact Timing Constraints
DAC, 1992.

DAC 1992

@inproceedings{DAC-1992-StollD,
	acmid         = "113938.149396",
	author        = "A. Stoll and Peter Duzy",
	booktitle     = "{Proceedings of the 29th Design Automation Conference}",
	isbn          = "0-8186-2822-7",
	pages         = "188--193",
	publisher     = "{IEEE Computer Society Press}",
	title         = "{High-Level Synthesis from VHDL with Exact Timing Constraints}",
	year          = 1992,
}

A. Stoll, Peter DuzyHigh-Level Synthesis from VHDL with Exact Timing ConstraintsDAC, 1992.

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A. Stoll, Peter Duzy
High-Level Synthesis from VHDL with Exact Timing Constraints
DAC, 1992.