BibSLEIGH — Proceedings of the 29th Design Automation Conference

Daniel G. Schweikert
Proceedings of the 29th Design Automation Conference
DAC, 1992.

SYS

@proceedings{DAC-1992,
	acmid         = "113938",
	address       = "Anaheim, California, USA",
	editor        = "Daniel G. Schweikert",
	isbn          = "0-8186-2822-7",
	publisher     = "{IEEE Computer Society Press}",
	title         = "{Proceedings of the 29th Design Automation Conference}",
	year          = 1992,
}

Contents (131 items)

DAC-1992-KriplaniNH #estimation: Maximum Current Estimation in CMOS Circuits (HK, FNN, INH), pp. 2–7.
DAC-1992-JuS #incremental #simulation #using: Incremental Circuit Simulation Using Waveform Relaxation (YCJ, RAS), pp. 8–11.
DAC-1992-JohnsonR #feedback #parallel: Parallel Waveform Relaxation of Circuits with Global Feedback Loops (TAJ, AER), pp. 12–15.
DAC-1992-ChengM #algorithm #on the #problem: On the Over-Specification Problem in Sequential ATPG Algorithms (KTC, HKTM), pp. 16–21.
DAC-1992-AbramoviciRM #approach #exclamation #testing: Freeze!: A New Approach for Testing Sequential Circuits (MA, KBR, DTM), pp. 22–25.
DAC-1992-LeeNB #generative #named #testing: SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits (KJL, CN, MAB), pp. 26–29.
DAC-1992-SarabiP #canonical #network #performance: Fast Exact and Quasi-Minimal Minimization of Highly Testable Fixed-Polarity AND/XOR Canonical Networks (AS, MAP), pp. 30–35.
DAC-1992-CoudertM #incremental: Implicit and Incremental Computation of Primes and Essential Primes of Boolean Functions (OC, JCM), pp. 36–39.
DAC-1992-LinCM #generative #multi: Symbolic Prime Generation for Multiple-Valued Functions (BL, OC, JCM), pp. 40–44.
DAC-1992-HillD #design: FPGA Design Principles (DDH, ED), pp. 45–46.
DAC-1992-CongHK: Net Partitions Yield Better Module Partitions (JC, LWH, ABK), pp. 47–52.
DAC-1992-ShihKT #clustering #multi: Performance-Driven System Partitioning on Multi-Chip Modules (MS, ESK, RST), pp. 53–56.
DAC-1992-HamadaCC #equation #estimation: A Wire Length Estimation Technique Utilizing Neighborhood Density Equations (TH, CKC, PMC), pp. 57–61.
DAC-1992-WangW #graph #optimisation: A Graph Theoretic Technique to Speed up Floorplan Area Optimization (TCW, DFW), pp. 62–68.
DAC-1992-Sur-KolayB #canonical: Canonical Embedding of Rectangular Duals with Applications to VLSI Floorplanning (SSK, BBB), pp. 69–74.
DAC-1992-RoychowdhuryNP #linear #simulation: Simulating Lossy Interconnect with High Frequency Nonidealities in Linear Time (JSR, ARN, DOP), pp. 75–80.
DAC-1992-LinK #simulation: Transient Simulation of Lossy Interconnect (SL, ESK), pp. 81–86.
DAC-1992-RaghavanBR #named #performance #problem #simulation: AWESpice: A General Tool for the Accurate and Efficient Simulation of Interconnect Problems (VR, JEB, RAR), pp. 87–92.
DAC-1992-LingKW #3d #approach #bound #simulation: A Boundary-Element Approach to Transient simulation of Three-Dimensional Integrated Circuit Interconnect (DDL, SK, JW), pp. 93–98.
DAC-1992-NouraniP #automation #scheduling #synthesis: Move Frame Scheduling and Mixed Scheduling-Allocation for the Automated Synthesis of Digital Systems (MN, CAP), pp. 99–105.
DAC-1992-RimJ #branch #representation #synthesis: Representing Conditional Branches for High-Level Synthesis Applications (MR, RJ), pp. 106–111.
DAC-1992-WakabayashiT #dependence #independence #scheduling: Global Scheduling Independent of Control Dependencies Based on Condition Vectors (KW, HT), pp. 112–115.
DAC-1992-Gebotys #embedded #scheduling: Optimal Scheduling and Allocation of Embedded VLSI Chips (CHG), pp. 116–119.
DAC-1992-RimJL #synthesis: Optimal Allocation and Binding in High-Level Synthesis (MR, RJ, RDL), pp. 120–123.
DAC-1992-GeurtsCM #throughput: Time Constrained Allocation and Assignment Techniques for High Throughput Signal Processing (WG, FC, HDM), pp. 124–127.
DAC-1992-BeckerST #hardware: An Engineering Environment for Hardware/Software Co-Simulation (DB, RKS, SGT), pp. 129–134.
DAC-1992-HuangD #compilation #pipes and filters #set #synthesis: High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers (IJH, AMD), pp. 135–140.
DAC-1992-KimBCP #algorithm #named: APT: An Area-Performance-Testability Driven Placement Algorithm (SK, PB, VC, JHP), pp. 141–146.
DAC-1992-GaoVL #algorithm #performance: A Performance Driven Macro-Cell Placement Algorithm (TG, PMV, CLL), pp. 147–152.
DAC-1992-LinS #approach #fuzzy #logic #problem: Fuzzy Logic Approach to Placement Problem (RBL, ES), pp. 153–158.
DAC-1992-BhattacharyaAA #fault #generative #testing #using: Delay Fault Test Generation for Scan/Hold Circuits Using Boolean Expressions (DB, PA, VDA), pp. 159–164.
DAC-1992-ChakrabortyAB #fault #generative #logic #modelling #random #testing: Delay Fault Models and Test Generation for Random Logic Sequential Circuits (TJC, VDA, MLB), pp. 165–172.
DAC-1992-SaldanhaBS #equivalence #generative #robust #testing: Equivalence of Robust Delay-Fault and Single Stuck-Fault Test Generation (AS, RKB, ALSV), pp. 173–176.
DAC-1992-PomeranzR #testing: At-Speed Delay Testing of Synchronous Sequential Circuits (IP, SMR), pp. 177–181.
DAC-1992-WolfTHMW #behaviour #synthesis: The Princeton University Behavioral Synthesis System (WW, AT, CYH, RM, EW), pp. 182–187.
DAC-1992-StollD #constraints #synthesis: High-Level Synthesis from VHDL with Exact Timing Constraints (AS, PD), pp. 188–193.
DAC-1992-SeawrightB #specification #synthesis: Synthesis from Production-Based Specifications (AS, FB), pp. 194–199.
DAC-1992-ChiproutN #analysis #network: Generalized Moment-Matching Methods for Transient Analysis of Interconnect Networks (EC, MSN), pp. 201–206.
DAC-1992-AnastasakisGKP #approximate #evaluation #on the: On the Stability of Moment-Matching Approximations in Asymptotic Waveform Evaluation (DFA, NG, SYK, LTP), pp. 207–212.
DAC-1992-LeeR #analysis #evaluation #linear #named #using: AWEsymbolic: Compiled Analysis of Linear(ized) Circuits using Asymptotic Waveform Evaluation (JYL, RAR), pp. 213–218.
DAC-1992-VahidG #clustering #design #specification: Specification Partitioning for System Design (FV, DG), pp. 219–224.
DAC-1992-GuptaCM #component #hardware #simulation #synthesis: Synthesis and Simulation of Digital Systems Containing Interacting Hardware and Software Components (RKG, CJNCJ, GDM), pp. 225–230.
DAC-1992-HungP #constraints #design #multi #synthesis: High-Level Synthesis with Pin Constraints for Multiple-Chip Designs (YHH, ACP), pp. 231–234.
DAC-1992-RaoK #clustering: Partitioning by Regularity Extraction (DSR, FJK), pp. 235–238.
DAC-1992-YuS #approach #design: A Path-Oriented Approach for Reducing Hazards in Asynchronous Designs (MLY, PAS), pp. 239–244.
DAC-1992-SaldanhaBS92a #algorithm #revisited: Circuit Structure Relations to Redundancy and Delay: The KMS Algorithm Revisited (AS, RKB, ALSV), pp. 245–248.
DAC-1992-ChenDC: Circuit Enhancement by Eliminating Long False Paths (HCC, DHCD, SWC), pp. 249–252.
DAC-1992-GhoshDKW #estimation #process: Estimation of Average Switching Activity in Combinational and Sequential Circuits (AG, SD, KK, JW), pp. 253–259.
DAC-1992-LeeP #constraints #functional #generative #testing: Hierarchical Test Generation under Intensive Global Functional Constraints (JL, JHP), pp. 261–266.
DAC-1992-SantucciDGB #behaviour #generative: A Methodology to Reduce the Computational Cost of Behavioral Test Pattern Generation (JFS, GD, NG, MB), pp. 267–272.
DAC-1992-VishakantaiahAA #automation: Automatic Test Knowledge Extraction from VHDL (ATKET) (PV, JAA, MSA), pp. 273–278.
DAC-1992-KrishnamoorthyN #using: Data Path Allocation using an Extended Binding Model (GK, JAN), pp. 279–284.
DAC-1992-GregoryMF #named #performance #resource management: ISIS: A System for Performance Driven Resource Sharing (BG, DM, DF), pp. 285–290.
DAC-1992-RundensteinerG #functional #optimisation #synthesis #using: Functional Synthesis Using Area and Delay Optimization (EAR, DG), pp. 291–296.
DAC-1992-Langeler #design: Directions to Watch in Design Technology (GL), p. 298.
DAC-1992-BatraC #comparison #named: Hcompare: A Hierarchical Netlist Comparison Program (PB, DC), pp. 299–304.
DAC-1992-Peltz #design #interpreter: An Interpreter for General Netlist Design Rule Checking (GP), pp. 305–310.
DAC-1992-BamjiV #design #using: Hierarchical Pitchmatching Compaction Using Minimum Design (CB, RV), pp. 311–317.
DAC-1992-Boyer #constraints #graph #independence #process: Process Independent Constraint Graph Compaction (DGB), pp. 318–322.
DAC-1992-KimLS #graph #layout #modelling #using: A New Hierarchical Layout Compactor Using Simplified Graph Models (WK, JL, HS), pp. 323–326.
DAC-1992-LeeR92a #concurrent #fault #on the #performance #simulation: On Efficient Concurrent Fault Simulation for Synchronous Sequential Circuits (DHL, SMR), pp. 327–331.
DAC-1992-BoseA #concurrent #fault #logic #memory management #message passing #multi #simulation: Concurrent Fault Simulation of Logic Gates and Memory Blocks on Message Passing Multicomputers (SB, PA), pp. 332–335.
DAC-1992-LeeH #fault #named #parallel #performance: HOPE: An Efficient Parallel Fault Simulator for Synchronous Sequential Circuits (HKL, DSH), pp. 336–340.
DAC-1992-MajumdarS #fault #on the #random testing #testing: On the Distribution of Fault Coverage and Test length in Random Testing of Combinational Circuits (AM, SS), pp. 341–346.
DAC-1992-KubiakPFS #evaluation: Exact Evaluation of Diagnostic Test Resolution (KK, SP, WKF, RAS), pp. 347–352.
DAC-1992-ChakravartyL #algorithm #fault #monitoring: Algorithms for Current Monitor Based Diagnosis of Bridging and Leakage Faults (SC, ML), pp. 353–356.
DAC-1992-GirardLP #approach #novel: A Novel Approach to Delay-Fault Diagnosis (PG, CL, SP), pp. 357–360.
DAC-1992-ChungR #architecture #named: TEMPT: Technology Mapping for the Exploration of FPGA Architectures with Hard-Wired Connections (KC, JR), pp. 361–367.
DAC-1992-SawkarT #array #programmable: Area and Delay Mapping for Table-Look-Up Based Field Programmable Gate Arrays (PS, DET), pp. 368–373.
DAC-1992-SchlichtmannBH #agile: Characterization of Boolean Functions for Rapid Matching in FPGA Technology Mapping (US, FB, MH), pp. 374–379.
DAC-1992-MurgaiBS #algorithm #multi #synthesis: An Improved Synthesis Algorithm for Multiplexor-Based PGA’s (RM, RKB, ALSV), pp. 380–386.
DAC-1992-HefferanS #maintenance #state of the art: Acquiring and Maintaining State-of-the-Art DA Systems (PMH, SS), pp. 387–392.
DAC-1992-LinLE: Analyzing Cycle Stealing on Synchronous Circuits with Level-Sensitive Latches (IL, JAL, KE), pp. 393–398.
DAC-1992-Szymanski: Computing Optimal Clock Schedules (TGS), pp. 399–404.
DAC-1992-ShenoySBS #equivalence #on the: On the Temporal Equivalence of Sequential Circuits (NVS, KJS, RKB, ALSV), pp. 405–409.
DAC-1992-AmonB #approach #verification: An Approach to Symbolic Timing Verification (TA, GB), pp. 410–413.
DAC-1992-GennartL #simulation #using #validation: Validating Discrete Event Simulations Using Event Pattern Mappings (BAG, DCL), pp. 414–419.
DAC-1992-LeeM #logic #multi #simulation: Two New Techniques for Compiled Multi-Delay Logic Simulation (YSL, PMM), pp. 420–423.
DAC-1992-Jones #incremental: Zero Delay versus Positive Delay in an Incremental Switch-Level Simulator (LGJ), pp. 424–427.
DAC-1992-Hirose #evaluation #logic #performance #simulation: Performance Evaluation of an Event-Driven Logic Simulation Machine (FH), pp. 428–431.
DAC-1992-ZeinED #logic #named: HLSIM — A New Hierarchical Logic Simulator and Netlist Converter (DAZ, OPE, GSD), pp. 432–437.
DAC-1992-HsuS #algebra #logic #multi #synthesis: Coalgebraic Division for Multilevel Logic Synthesis (WJH, WZS), pp. 438–442.
DAC-1992-ChenF #algorithm #logic #optimisation #performance #set: Efficient Sum-to-One Subsets Algorithm for Logic Optimization (KCC, MF), pp. 443–448.
DAC-1992-Malik #multi #network #optimisation #using: Optimization of Primitive Gate Networks Using Multiple Output Two-Level Minimization (AAM), pp. 449–453.
DAC-1992-BatekH #logic: Test-Set Preserving Logic Transformations (MJB, JPH), pp. 454–458.
DAC-1992-RuehliH #analysis #challenge: Challenges and Advances in Electrical Interconnect Analysis (AER, HH), pp. 460–465.
DAC-1992-FranzonSSBMM #generative #tool support: Tools to Aid in Wiring Rule Generation for High Speed Interconnects (PDF, SS, MBS, MB, SM, TM), pp. 466–471.
DAC-1992-ChangCLLO #design #named #performance: IPDA: Interconnect Performance Design Assistant (NHC, KJC, JL, KL, SYO), pp. 472–477.
DAC-1992-LiLAS #implementation #on the #problem: On the Circuit Implementation Problem (WNL, AL, PA, SS), pp. 478–483.
DAC-1992-KungDNG #algorithm #named: BDDMAP: A Technology Mapper Based on a New Covering Algorithm (DSK, RFD, TAN, DJG), pp. 484–487.
DAC-1992-Fishburn #heuristic #logic #named: LATTIS: An Iterative Speedup Heuristic for Mapped Logic (JPF), pp. 488–491.
DAC-1992-ChaudharyP #algorithm #constraints: A Near Optimal Algorithm for Technology Mapping Minimizing Area under Delay Constraints (KC, MP), pp. 492–498.
DAC-1992-JacomeD #design #framework #process: Design Process Management for CAD Frameworks (MFJ, SWD), pp. 500–505.
DAC-1992-BeggsSCE #automation #design: Automated Design Decision Support System (RB, JS, CC, JE), pp. 506–511.
DAC-1992-PyoSHPKTCCLWD #automation #design: Application-Driven Design Automation for Microprocessor Design (IP, CLS, IJH, KRP, YSK, CYT, HTC, GC, SL, SW, AMD), pp. 512–517.
DAC-1992-ChaoHH: Zero Skew Clock Net Routing (THC, YCH, JMH), pp. 518–523.
DAC-1992-MitsuhashiK #network #optimisation: Power and Ground Network Topology Optimization for Cell Based VLSIs (TM, ESK), pp. 524–529.
DAC-1992-HongHCK #algorithm #named #performance: FARM: An Efficient Feed-Through Pin Assignment Algorithm (XH, JH, CKC, ESK), pp. 530–535.
DAC-1992-Frankle #adaptation #layout: Iterative and Adaptive Slack Allocation for Performance-Driven Layout and FPGA Routing (JF), pp. 536–542.
DAC-1992-ChengCDL #optimisation #performance: The Role of Long and Short Paths in Circuit Performance Optimization (SWC, HCC, DHCD, AL), pp. 543–548.
DAC-1992-DevadasKMW #logic #verification: Certified Timing Verification and the Transition Delay of a Logic Circuit (SD, KK, SM, ARW), pp. 549–555.
DAC-1992-DamianiM #equation #logic #optimisation: Recurrence Equations and the Optimization of Synchronous Logic Circuits (MD, GDM), pp. 556–561.
DAC-1992-ChakradharKA #fault tolerance #finite #state machine #synthesis: Finite State Machine Synthesis with Fault Tolerant Test Function (STC, SK, VDA), pp. 562–567.
DAC-1992-LavagnoMBS #graph #problem: Solving the State Assignment Problem for Signal Transition Graphs (LL, CWM, RKB, ALSV), pp. 568–572.
DAC-1992-PomeranzC #using: State Assignment Using Input/Output Functions (IP, KTC), pp. 573–577.
DAC-1992-FangFL #approach #multi #performance #problem: A New Efficient Approach to Multilayer Channel Routing Problem (SCF, WSF, SLL), pp. 579–584.
DAC-1992-FujiiMMY #multi: A Multi-Layer Channel Router with New Style of Over-the-Cell Routing (TF, YM, TM, TY), pp. 585–588.
DAC-1992-Ho #modelling: New Models for Four- and Five-Layer Channel Routing (TTH), pp. 589–593.
DAC-1992-HouC #algorithm #permutation: A Pin Permutation Algorithm for Improving Over-the-Cell Channel Routing (CYH, CYRC), pp. 594–599.
DAC-1992-NatarajanSHS #performance: Over-the-Cell Channel Routing for High Performance Circuits (SN, NAS, NDH, MS), pp. 600–603.
DAC-1992-WuSHS: Over-the-Cell Routers for New Cell Model (BW, NAS, NDH, MS), pp. 604–607.
DAC-1992-LaiS #diagrams #multi #verification: Edge-Valued Binary Decision Diagrams for Multi-Level Hierarchical Verification (YTL, SS), pp. 608–613.
DAC-1992-CabodiCCGPR #traversal: A New Model for Improving symbolic Product Machine Traversal (GC, PC, FC, SG, PP, MSR), pp. 614–619.
DAC-1992-PixleyJH #diagrams #sequence: Exact Calculation of Synchronization Sequences Based on Binary Decision Diagrams (CP, SWJ, GDH), pp. 620–623.
DAC-1992-MercerKR #functional #generative #order #performance: Functional Approaches to Generating Orderings for Efficient Symbolic Representations (MRM, RK, DER), pp. 624–627.
DAC-1992-RhoS #induction #verification: Inductive Verification of Iterative Systems (JKR, FS), pp. 628–633.
DAC-1992-LeongB #automation #generative #interface #modelling: The Automatic Generation of Bus-Interface Models (YHL, WPB), pp. 634–637.
DAC-1992-PrabhuP #synthesis: Superpipelined Control and Data Path Synthesis (UP, BMP), pp. 638–643.
DAC-1992-DuttaRV #distributed #synthesis: Distributed Design-Space Exploration for High-Level Synthesis Systems (RD, JR, RV), pp. 644–650.
DAC-1992-PuriG #algorithm #performance: An Efficient algorithm for Microword Length Minimization (RP, JG), pp. 651–656.
DAC-1992-BergamaschiLK #behaviour #optimisation #synthesis #using: Control Optimization in High-Level Synthesis Using Behavioral Don’t Cares (RAB, DAL, AK), pp. 657–661.
DAC-1992-KarriO #fault tolerance #synthesis: Transformation-Based High-Level Synthesis of Fault-Tolerant ASICs (RK, AO), pp. 662–665.
DAC-1992-KahnG #design: The Electronic Design Interchange Format EDIF: Present and Future (HJK, RG), pp. 666–671.
DAC-1992-Scallan #framework #perspective: CAD Framework Initiative — A User Perspective (TJS), pp. 672–675.
DAC-1992-OkudaO #algorithm #generative #layout #performance: An Efficient Routing Algorithm for SOG Cell Generation on a Dense Gate-Isolated Layout Style (RO, SO), pp. 676–681.
DAC-1992-LiaoC #layout #synthesis: Routing Considerations in Symbolic Layout Synthesis (YL, SC), pp. 682–686.
DAC-1992-KimOI #generative #performance: Experiments with a Performance Driven Module Generator (SK, RMO, MJI), pp. 687–690.
DAC-1992-Palczewski #parallel: Plane Parallel a Maze Router and Its Application to FPGAs (MP), pp. 691–697.
DAC-1992-MaulikCR #approach #programming #synthesis: A Mixed-Integer Nonlinear Programming Approach to Analog Circuit Synthesis (PCM, LRC, RAR), pp. 698–703.
DAC-1992-DharchoudhuryK #approach #design #optimisation #worst-case: An Integrated Approach to Realistic Worst-Case Design Optimization of MOS Analog Circuits (AD, SMK), pp. 704–709.
DAC-1992-NaborsW #3d #algorithm #multi: Multipole-Accelerated 3-D Capacitance Extraction Algorithms for Structures with Conformal Dielectrics (KN, JW), pp. 710–715.

Daniel G. SchweikertProceedings of the 29th Design Automation ConferenceDAC, 1992.

Contents (131 items)

Daniel G. Schweikert
Proceedings of the 29th Design Automation Conference
DAC, 1992.