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Travelled to:
1 × USA
Collaborated with:
P.Duzy
Talks about:
constraint (1) synthesi (1) level (1) exact (1) vhdl (1) time (1) high (1)

Person: A. Stoll

DBLP DBLP: Stoll:A=

Contributed to:

DAC 19921992

Wrote 1 papers:

DAC-1992-StollD #constraints #synthesis
High-Level Synthesis from VHDL with Exact Timing Constraints (AS, PD), pp. 188–193.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.