CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells
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Avaneendra Gupta, John P. Hayes
CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells
DAC, 1997.

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@inproceedings{DAC-1997-GuptaH,
	author        = "Avaneendra Gupta and John P. Hayes",
	booktitle     = "{Proceedings of the 34th Design Automation Conference}",
	doi           = "10.1145/266021.266198",
	isbn          = "0-89791-920-3",
	pages         = "452--455",
	publisher     = "{ACM Press}",
	title         = "{CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells}",
	year          = 1997,
}

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