Proceedings of the 34th Design Automation Conference
BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
EDIT!
CC-BY
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter

Ellen J. Yoffa, Giovanni De Micheli, Jan M. Rabaey
Proceedings of the 34th Design Automation Conference
DAC, 1997.

SYS
DBLP
Scholar
Full names Links ISxN
@proceedings{DAC-1997,
	acmid         = "266021",
	address       = "Anaheim, California, USA",
	editor        = "Ellen J. Yoffa and Giovanni De Micheli and Jan M. Rabaey",
	isbn          = "0-89791-920-3",
	publisher     = "{ACM Press}",
	title         = "{Proceedings of the 34th Design Automation Conference}",
	year          = 1997,
}

Contents (140 items)

DAC-1997-MaheshwariS #algorithm
An Improved Algorithm for Minimum-Area Retiming (NM, SSS), pp. 2–7.
DAC-1997-SentovichTB #optimisation #performance #set #using
Efficient Latch Optimization Using Exclusive Sets (ES, HT, GB), pp. 8–11.
DAC-1997-MarculescuMP #analysis #finite #probability #sequence #state machine
Sequence Compaction for Probabilistic Analysis of Finite-State Machines (DM, RM, MP), pp. 12–15.
DAC-1997-SemenovYPPC #independence #synthesis
Synthesis of Speed-Independent Circuits from STG-Unfolding Segment (ALS, AY, EP, MAP, JC), pp. 16–21.
DAC-1997-BeniniMP #adaptation #design #latency #pipes and filters #throughput
Telescopic Units: Increasing the Average Throughput of Pipelined Designs by Adaptive Latency Control (LB, EM, MP), pp. 22–27.
DAC-1997-ElfadelL #modelling #network
Zeros and Passivity of Arnoldi-Reduced-Order Models for Interconnect Networks (IME, DDL), pp. 28–33.
DAC-1997-KernsY #congruence #network #reduction
Preservation of Passivity During RLC Network Reduction via Split Congruence Transformations (KJK, ATY), pp. 34–39.
DAC-1997-NaborsFCK #modelling
Lumped Interconnect Models Via Gaussian Quadrature (KN, TTF, HWC, KSK), pp. 40–45.
DAC-1997-DartuP #worst-case
Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling (FD, LTP), pp. 46–51.
DAC-1997-BalarinS #embedded #realtime #validation
Schedule Validation for Embedded Reactive Real-Time Systems (FB, ALSV), pp. 52–57.
DAC-1997-Tirat-GefenSP #design #multi
Incorporating Imprecise Computation into System-Level Design of Application-Specific Heterogeneous Multiprocessors (YGTG, DCdSJ, ACP), pp. 58–63.
DAC-1997-AdeLP #data flow #graph #memory management
Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA Targets (MA, RL, JAP), pp. 64–69.
DAC-1997-LiaoTG #design #hardware #implementation #modelling #performance
An Efficient Implementation of Reactivity for Modeling Hardware in the Scenic Design Environment (SYL, SWKT, RKG), pp. 70–75.
DAC-1997-Frenkil #design #power management #tool support
Tools and Methodologies for Low Power Design (JF), pp. 76–81.
DAC-1997-YimHPCYOPK #design #verification
A C-Based RTL Design Verification Methodology for Complex Microprocessor (JSY, YHH, CJP, HC, WSY, HSO, ICP, CMK), pp. 83–88.
DAC-1997-WalterLDLMKW #approach #multi #random #simulation #verification
Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors (JAW, JL, GD, BL, HJM, KWK, BW), pp. 89–94.
DAC-1997-RainaBNMB #design #performance #testing
Efficient Testing of Clock Regenerator Circuits in Scan Designs (RR, RB, CN, RFM, CB), pp. 95–100.
DAC-1997-FangWY #debugging #online #realtime
A Real-Time RTL Engineering-Change Method Supporting On-Line Debugging for Logic-Emulation Applications (WJF, ACHW, TYY), pp. 101–106.
DAC-1997-YeR #algorithm #graph #network #synthesis
A Graph-Based Synthesis Algorithm for AND/XOR Networks (YY, KR), pp. 107–112.
DAC-1997-LiuSAS #black box #design #optimisation
Optimizing Designs Containing Black Boxes (THL, KS, AA, VS), pp. 113–116.
DAC-1997-LiaoD #bound #problem #using
Solving Covering Problems Using LPR-Based Lower Bounds (SYL, SD), pp. 117–120.
DAC-1997-Coudert #graph
Exact Coloring of Real-Life Graphs is Easy (OC), pp. 121–126.
DAC-1997-DengiR #2d #modelling
Hierarchical 2-D Field Solution for Capacitance Extraction for VLSI Interconnect Modeling (EAD, RAR), pp. 127–132.
DAC-1997-BeattieP #bound
Bounds for BEM Capacitance Extraction (MWB, LTP), pp. 133–136.
DAC-1997-HeCP #named
SPIE: Sparse Partial Inductance Extraction (ZH, MC, LTP), pp. 137–140.
DAC-1997-KapurZ #parametricity #performance
A Fast Method of Moments Solver for Efficient Parameter Extraction of MCMs (SK, JZ), pp. 141–146.
DAC-1997-MalikML #analysis #embedded
Static Timing Analysis of Embedded Software (SM, MM, YTSL), pp. 147–152.
DAC-1997-LiW #memory management #multi #synthesis
A Task-Level Hierarchical Memory Model for System Synthesis of Multiprocessors (YL, WW), pp. 153–156.
DAC-1997-SambandamH #architecture #behaviour #design #embedded #predict #realtime
Predicting Timing Behavior in Architectural Design Exploration of Real-Time Embedded Systems (RSS, XH), pp. 157–160.
DAC-1997-NelsonJB #execution #verification
Formal Verification of a Superscalar Execution Unit (KLN, AJ, REB), pp. 161–166.
DAC-1997-PandeyRBA #evaluation #using #verification
Formal Verification of Content Addressable Memories Using Symbolic Trajectory Evaluation (MP, RR, REB, MSA), pp. 167–172.
DAC-1997-JangQKP #case study #verification
Formal Verification of FIRE: A Case Study (JYJ, SQ, MK, CP), pp. 173–177.
DAC-1997-RowsonS #design #interface
Interface-Based Design (JAR, ALSV), pp. 178–183.
DAC-1997-KlenkeMAJRG #analysis #dependence #design #performance
An Integrated Design Environment for Performance and Dependability Analysis (RHK, MM, JHA, BWJ, RR, AG), pp. 184–189.
DAC-1997-BentzRL #design #estimation
A Dynamic Design Estimation and Exploration Environment (OB, JMR, DL), pp. 190–195.
DAC-1997-ManneGS #locality #memory management
Remembrance of Things Past: Locality and Memory in BDDs (SM, DG, FS), pp. 196–201.
DAC-1997-MeinelST #diagrams #linear
Linear Sifting of Decision Diagrams (CM, FS, TT), pp. 202–207.
DAC-1997-HongBBM #using
Safe BDD Minimization Using Don’t Cares (YH, PAB, JRB, KLM), pp. 208–213.
DAC-1997-LillisC #multi #optimisation
Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater Insertion (JL, CKC), pp. 214–219.
DAC-1997-KukimotoB #analysis #detection
Exact Required Time Analysis via False Path Detection (YK, RKB), pp. 220–225.
DAC-1997-AmonBHL #diagrams #using #verification
Symbolic Timing Verification of Timing Diagrams using Presburger Formulas (TA, GB, TH, JL), pp. 226–231.
DAC-1997-Marwedel #code generation
Code Generation for Core Processors (PM), pp. 232–237.
DAC-1997-DagaS #design #interface #verification
Interface Timing Verification Drives System Design (AJD, PS), pp. 240–245.
DAC-1997-ShacklefordYOKTY #design #embedded #optimisation
Memory-CPU Size Optimization for Embedded System Designs (BS, MY, EO, HK, HT, HY), pp. 246–251.
DAC-1997-PotkonjakKK #behaviour #case study #design
Methodology for Behavioral Synthesis-Based Algorithm-Level Design Space Exploration: DCT Case Study (MP, KK, RK), pp. 252–257.
DAC-1997-Kurshan #verification
Formal Verification in a Commercial Setting (RPK), pp. 258–262.
DAC-1997-KuehlmannK #equivalence #using
Equivalence Checking Using Cuts and Heaps (AK, FK), pp. 263–268.
DAC-1997-Roychowdhury #multi #performance #simulation
Efficient Methods for Simulating Highly Nonlinear Multi-Rate Circuits (JSR), pp. 269–274.
DAC-1997-TianS #agile #fault #parametricity #simulation
Rapid Frequency-Domain Analog Fault Simulation Under Parameter Tolerances (MWT, CJRS), pp. 275–280.
DAC-1997-MirROPH #automation #evaluation #fault #named #simulation
SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems (SM, AR, TO, EJP, JLH), pp. 281–286.
DAC-1997-SudarsanamLD #analysis #architecture #evaluation
Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures (AS, SYL, SD), pp. 287–292.
DAC-1997-WillemsBKGM #approach #design #fixpoint
System Level Fixed-Point Design Based on an Interpolative Approach (MW, VB, HK, TG, HM), pp. 293–298.
DAC-1997-HadjiyiannisHD #named #set
ISDL: An Instruction Set Description Language for Retargetability (GH, SH, SD), pp. 299–302.
DAC-1997-HartoogRRDDHK #generative #hardware #tool support
Generation of Software Tools from Processor Descriptions for Hardware/Software Codesign (MRH, JAR, PDR, SD, DDD, EAH, NK), pp. 303–306.
DAC-1997-Man #education #question
Education for the Deep Submicron Age: Business as Usual? (HDM), pp. 307–312.
DAC-1997-Brodersen #design #empirical #integration #named
InfoPad — An Experiment in System Level Design and Integration (RWB), pp. 313–314.
DAC-1997-SmailagicSMS #agile #case study #design #off the shelf #prototype #smarttech
Very Rapid Prototyping of Wearable Computers: A Case Study of Custom versus Off-the-Shelf Design Methodologies (AS, DPS, RM, JS), pp. 315–320.
DAC-1997-HeinekenKMNOP #interface
CAD at the Design-Manufacturing Interface (HTH, JK, WM, PKN, CHO, WAP), pp. 321–326.
DAC-1997-GuruswamyMDRCFJ #automation #layout #library #named #standard #synthesis
CELLERITY: A Fully Automatic Layout Synthesis System for Standard Cell Libraries (MG, RLM, DD, SR, VC, AF, LGJ), pp. 327–332.
DAC-1997-BaltusVADM #concurrent #generative #library #standard
Developing a Concurrent Methodology for Standard-Cell Library Generation (DGB, TV, RCA, JD, TGM), pp. 333–336.
DAC-1997-CroixW #logic #performance #synthesis
A Fast And Accurate Technique To Optimize Characterization Tables For Logic Synthesis (JFC, DFW), pp. 337–340.
DAC-1997-LiG #exception #modelling #optimisation
Limited Exception Modeling and Its Use in Presynthesis Optimizations (JL, RKG), pp. 341–346.
DAC-1997-HongKP #statistics
Potential-Driven Statistical Ordering of Transformations (IH, DK, MP), pp. 347–352.
DAC-1997-KimKP #programmable #synthesis
Synthesis of Application Specific Programmable Processors (KK, RK, MP), pp. 353–358.
DAC-1997-WalrathV #evaluation #modelling #performance #symbolic computation #trade-off #visualisation
Symbolic Evaluation of Performance Models for Tradeoff Visualization (JW, RV), pp. 359–364.
DAC-1997-GuptaN #estimation #megamodelling
Power Macromodeling for High Level Power Estimation (SG, FNN), pp. 365–370.
DAC-1997-DingWHP #cumulative #estimation #statistics
Statistical Estimation of the Cumulative Distribution Function for Power Dissipation in VLSI Cirucits (CSD, QW, CTH, MP), pp. 371–376.
DAC-1997-YuanTK #estimation #statistics
Statistical Estimation of Average Power Dissipation in Sequential Circuits (LPY, CCT, SMK), pp. 377–382.
DAC-1997-KrsticC #generative
Vector Generation for Maximum Instantaneous Current Through Supply Lines for CMOS Circuits (AK, KTC), pp. 383–388.
DAC-1997-PasseroneLCS #analysis #hardware #performance #prototype #trade-off
Fast Hardware/Software Co-Simulation for Virtual Prototyping and Trade-Off Analysis (CP, LL, MC, ALSV), pp. 389–394.
DAC-1997-HinesB #communication #embedded #modelling
Dynamic Communication Models in Embedded System Co-Simulation (KH, GB), pp. 395–400.
DAC-1997-PantDC #energy #logic #network #optimisation #power management #random
Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks (PP, VD, AC), pp. 403–408.
DAC-1997-KaoCA #multi
Transistor Sizing Issues and Tool For Multi-Threshold CMOS Technology (JK, AC, DA), pp. 409–414.
DAC-1997-XanthopoulosYC #architecture #case study #estimation #using
Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT (TX, YY, AC), pp. 415–420.
DAC-1997-TsuiCWDP #design #estimation #framework #power management #video
A Power Estimation Framework for Designing Low Power Portable Video Applications (CYT, KKC, QW, CSD, MP), pp. 421–424.
DAC-1997-WangVG #trade-off
An Investigation of Power Delay Trade-Offs on PowerPC Circuits (QW, SBKV, SG), pp. 425–428.
DAC-1997-RaghunathanDJW #control flow #design #power management
Power Management Techniques for Control-Flow Intensive Designs (AR, SD, NKJ, KW), pp. 429–434.
DAC-1997-Gebotys #energy #memory management #network #using
Low Energy Memory and Register Allocation Using Network Flow (CHG), pp. 435–440.
DAC-1997-KimC #synthesis #using
Power-conscious High Level Synthesis Using Loop Folding (DK, KC), pp. 441–445.
DAC-1997-LefebvreMS #future of #generative #physics #synthesis
The Future of Custom Cell Generation in Physical Synthesis (ML, DM, CS), pp. 446–451.
DAC-1997-GuptaH #2d #generative #layout #named #optimisation
CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells (AG, JPH), pp. 452–455.
DAC-1997-KimK #algorithm #design #layout #performance
An Efficient Transistor Folding Algorithm for Row-Based CMOS Layout Design (JK, SMK), pp. 456–459.
DAC-1997-Lakos #layout
Technology Retargeting for IC Layout (JL), pp. 460–465.
DAC-1997-ChangLMAC #approach #synthesis
A Test Synthesis Approach to Reducing BALLAST DFT Overhead (DC, MTCL, MMS, TA, KTC), pp. 466–471.
DAC-1997-TsaiHRM #generative #named #random
STARBIST: Scan Autocorrelated Random Pattern Generation (KHT, SH, JR, MMS), pp. 472–477.
DAC-1997-TsaiCLB #algorithm #hybrid
A Hybrid Algorithm for Test Point Selection for Scan-Based BIST (HCT, KTC, CJL, SB), pp. 478–483.
DAC-1997-MeyerST #array #design #synthesis
Design and Synthesis of Array Structured Telecommunication Processing Applications (WM, AS, FT), pp. 486–491.
DAC-1997-HeinPK #prototype
RASSP Virtual Prototyping of DSP Systems (CH, JP, WK), pp. 492–497.
DAC-1997-Schneider #parallel #trade-off
A Parallel/Serial Trade-Off Methodology for Look-Up Table Based Decoders (CS), pp. 498–503.
DAC-1997-MaciiPS #estimation #modelling #optimisation
High-Level Power Modeling, Estimation, and Optimization (EM, MP, FS), pp. 504–511.
DAC-1997-KuoC #approach #clustering #network
A Network Flow Approach for Hierarchical Tree Partitioning (MTK, CKC), pp. 512–517.
DAC-1997-FangW #clustering #design #multi
Multi-Way FPGA Partitioning by Fully Exploiting Design Hierarchy (WJF, ACHW), pp. 518–521.
DAC-1997-KrupnovaAS #clustering
A Hierarchy-Driven FPGA Partitioning Method (HK, AA, GS), pp. 522–525.
DAC-1997-KarypisAKS #clustering #multi
Multilevel Hypergraph Partitioning: Application in VLSI Domain (GK, RA, VK, SS), pp. 526–529.
DAC-1997-AlpertHK #clustering #multi
Multilevel Circuit Partitioning (CJA, JHH, ABK), pp. 530–533.
DAC-1997-GhoshRJ #design #generative #testing
Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs (IG, AR, NKJ), pp. 534–539.
DAC-1997-GoodbyO
Frequency-Domain Compatibility in Digital Filter BIST (LG, AO), pp. 540–545.
DAC-1997-NouraniCP #fault #testing
A Scheme for Integrated Controller-Datapath Fault Testing (MN, JC, CAP), pp. 546–551.
DAC-1997-LavanaKBK #collaboration #design #execution #internet #paradigm #workflow
Executable Workflows: A Paradigm for Collaborative Design on the Internet (HL, AK, FB, KK), pp. 553–558.
DAC-1997-Cottrell #component
Electronic Component Information Exchange (ECIX) (DRC), pp. 559–563.
DAC-1997-SchurmannA #design #modelling #tool support
Modeling Design Tasks and Tools: The Link Between Product and Flow Model (BS, JA), pp. 564–569.
DAC-1997-MarculescuMP97a #estimation #sequence
Hierarchical Sequence Compaction for Power Estimation (RM, DM, MP), pp. 570–575.
DAC-1997-HsiehPMR #evaluation #synthesis
Profile-Driven Program Synthesis for Evaluation of System Power Dissipation (CTH, MP, GM, FR), pp. 576–581.
DAC-1997-RamprasadSH #estimation #process #statistics
Analytical Estimation of Transition Activity From Word-Level Signal Statistics (SR, NRS, INH), pp. 582–587.
DAC-1997-AlpertD
Wire Segmenting for Improved Buffer Insertion (CJA, AD), pp. 588–593.
DAC-1997-KahngT #bound
More Practical Bounded-Skew Clock Routing (ABK, CWAT), pp. 594–599.
DAC-1997-ChangC #approach #multi #performance
An Efficient Approach to Multi-Layer Layer Assignment with Application to Via Minimization (CCC, JC), pp. 600–603.
DAC-1997-ChenW
Optimal Wire-Sizing Function with Fringing Capacitance Consideration (CPC, DFW), pp. 604–607.
DAC-1997-PomeranzR #approach #fault #multi #simulation #using
Fault Simulation under the Multiple Observation Time Approach using Backward Implications (IP, SMR), pp. 608–613.
DAC-1997-WangG #testing
ATPG for Heat Dissipation Minimization During Scan Testing (SW, SKG), pp. 614–619.
DAC-1997-RoigCPP #automation #generative
Automatic Generation of Synchronous Test Patterns for Asynchronous Circuits (OR, JC, MAP, EP), pp. 620–625.
DAC-1997-CongHKNSY #2d #analysis
Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology (JC, LH, ABK, DN, NS, SHCY), pp. 627–632.
DAC-1997-ForzanFG #megamodelling #performance #standard
Accurate and Efficient Macromodel of Submicron Digital Standard Cells (CF, BF, CG), pp. 633–637.
DAC-1997-ChenL #analysis #design #power management
Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design (HHC, DDL), pp. 638–643.
DAC-1997-CongW #pipes and filters #synthesis
FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits (JC, CW), pp. 644–649.
DAC-1997-PandaN #power management #synthesis
Technology-Dependent Transformations for Low-Power Synthesis (RP, FNN), pp. 650–655.
DAC-1997-ChenHL #approach #design #power management #re-engineering
Low Power FPGA Design — A Re-engineering Approach (CSC, TH, CLL), pp. 656–661.
DAC-1997-JiangKCM #logic #optimisation #performance
Post-Layout Logic Restructuring for Performance Optimization (YMJ, AK, KTC, MMS), pp. 662–665.
DAC-1997-MurofushiIMM #layout #power management
Layout Driven Re-synthesis for Low Power Consumption LSIs (MM, TI, MM, TM), pp. 666–669.
DAC-1997-Tang #design #overview #process
Overview of Microelectromechanical Systems and Design Processes (WCT), pp. 670–673.
DAC-1997-KaramCBDPSRHG
CAD and Foundries for Microsystems (JMK, BC, HB, PD, AP, VS, MR, KH, MG), pp. 674–679.
DAC-1997-MukherjeeF #design
Structured Design of Microelectromechanical Systems (TM, GKF), pp. 680–685.
DAC-1997-AluruW #algorithm #simulation
Algorithms for Coupled Domain MEMS Simulation (NRA, JW), pp. 686–690.
DAC-1997-HenkelE #hardware #using
A Hardware/Software Partitioner Using a Dynamically Determined Granularity (JH, RE), pp. 691–696.
DAC-1997-KirovskiP #power management #realtime #synthesis
System-Level Synthesis of Low-Power Hard Real-Time Systems (DK, MP), pp. 697–702.
DAC-1997-DaveLJ #embedded #named
COSYN: Hardware-Software Co-Synthesis of Embedded Systems (BPD, GL, NKJ), pp. 703–708.
DAC-1997-AgrawalG #behaviour #clustering #data flow #embedded
Data-Flow Assisted Behavioral Partitioning for Embedded Systems (SA, RKG), pp. 709–712.
DAC-1997-BakshiG #clustering #hardware #pipes and filters
Hardware/Software Partitioning and Pipelining (SB, DG), pp. 713–716.
DAC-1997-Dai #verification
Chip Parasitic Extraction and Signal Integrity Verification (WWMD), pp. 717–719.
DAC-1997-GrundmannDAR #design #performance #using
Designing High Performance CMOS Microprocessors Using Full Custom Techniques (WJG, DD, RLA, NLR), pp. 722–727.
DAC-1997-CabodiCLQ #approach #clustering #effectiveness #scalability #traversal
Disjunctive Partitioning and Partial Iterative Squaring: An Effective Approach for Symbolic Traversal of Large Circuits (GC, PC, LL, SQ), pp. 728–733.
DAC-1997-HasteerMB #performance
An Efficient Assertion Checker for Combinational Properties (GH, AM, PB), pp. 734–739.
DAC-1997-GuptaMA #formal method #simulation #towards #using #validation
Toward Formalizing a Validation Methodology Using Simulation Coverage (AG, SM, PA), pp. 740–745.
DAC-1997-Vygen #algorithm #scalability
Algorithms for Large-Scale Flat Placement (JV), pp. 746–751.
DAC-1997-AlpertCHMY #polynomial #revisited
Quadratic Placement Revisited (CJA, TFC, DJHH, ILM, KY), pp. 752–757.
DAC-1997-SarrafzadehKT #unification
Unification of Budgeting and Placement (MS, DAK, GET), pp. 758–761.
DAC-1997-XuGC #clustering #refinement
Cluster Refinement for Block Placement (JX, PNG, CKC), pp. 762–765.
DAC-1997-LevitanMKRCFM #design
Computer-Aided Design of Free-Space Opto-Electronic Systems (SPL, PJM, TPK, MAR, DMC, CF, FBM), pp. 768–773.
DAC-1997-BauerE #approach #hardware
Hardware/Software Co-Simulation in a VHDL-Based Test Bench Approach (MB, WE), pp. 774–779.
DAC-1997-LiemCSPJGLFB #case study #development #embedded #multi
Am Embedded System Case Study: The Firm Ware Development Environment for a Multimedia Audio Processor (CL, MC, MS, PGP, AAJ, JMG, JL, XF, LB), pp. 780–785.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.