Igor Keller, King Ho Tam, Vinod Kariat
Challenges in gate level modeling for delay and SI at 65nm and below
DAC, 2008.
@inproceedings{DAC-2008-KellerTK, author = "Igor Keller and King Ho Tam and Vinod Kariat", booktitle = "{Proceedings of the 45th Design Automation Conference}", doi = "10.1145/1391469.1391590", isbn = "978-1-60558-115-6", pages = "468--473", publisher = "{ACM}", title = "{Challenges in gate level modeling for delay and SI at 65nm and below}", year = 2008, }