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Travelled to:
1 × USA
Collaborated with:
K.H.Tam V.Kariat
Talks about:
challeng (1) model (1) level (1) delay (1) below (1) gate (1)

Person: Igor Keller

DBLP DBLP: Keller:Igor

Contributed to:

DAC 20082008

Wrote 1 papers:

DAC-2008-KellerTK #challenge #modelling
Challenges in gate level modeling for delay and SI at 65nm and below (IK, KHT, VK), pp. 468–473.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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