BibSLEIGH — Proceedings of the 45th Design Automation Conference

Limor Fix
Proceedings of the 45th Design Automation Conference
DAC, 2008.

SYS

@proceedings{DAC-2008,
	acmid         = "1391469",
	address       = "Anaheim, California, USA",
	editor        = "Limor Fix",
	isbn          = "978-1-60558-115-6",
	publisher     = "{ACM}",
	title         = "{Proceedings of the 45th Design Automation Conference}",
	year          = 2008,
}

Contents (195 items)

DAC-2008-GolsonC #implementation #physics #theory and practice: Flow engineering for physical implementation: theory and practice (SG, PC), p. 1.
DAC-2008-Garland #gpu #manycore #matrix: Sparse matrix computations on manycore GPU’s (MG), pp. 2–6.
DAC-2008-MattsonW #parallel #programming #question: Parallel programming: can we PLEASE get it right this time? (TM, MW), pp. 7–11.
DAC-2008-CatanzaroKS #research: Parallelizing CAD: a timely research agenda for EDA (BCC, KK, BYS), pp. 12–17.
DAC-2008-CzajkowskiB #composition #linear #logic #synthesis: Functionally linear decomposition and synthesis of logic circuits for FPGAs (TSC, SDB), pp. 18–23.
DAC-2008-HuSMH #multi #reduction: FPGA area reduction by multi-output function based sequential resynthesis (YH, VS, RM, LH), pp. 24–29.
DAC-2008-HsuW #algorithm #memory management #network #power management: A generalized network flow based algorithm for power-aware FPGA memory mapping (TYH, TCW), pp. 30–33.
DAC-2008-EguroH #pipes and filters: Enhancing timing-driven FPGA placement for pipelined netlists (KE, SH), pp. 34–37.
DAC-2008-LiL #modelling #performance #statistics: Statistical regression for efficient high-dimensional modeling of analog and mixed-signal performance variations (XL, HL), pp. 38–43.
DAC-2008-DasV #adaptation #synthesis: Topology synthesis of analog circuits based on adaptively generated building blocks (AD, RV), pp. 44–49.
DAC-2008-LinL #clustering: Analog placement based on hierarchical module clustering (MPHL, SCL), pp. 50–55.
DAC-2008-BauerSH #embedded #runtime #set: Run-time instruction set selection in a transmutable embedded processor (LB, MS, JH), pp. 56–61.
DAC-2008-ChongP #agile #float #generative: Rapid application specific floating-point unit generation with bit-alignment (YJC, SP), pp. 62–67.
DAC-2008-HomayounPMV #embedded #energy #performance #scalability: Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency (HH, SP, MAM, AVV), pp. 68–71.
DAC-2008-ReshadiGG #case study #design #internet #protocol: C-based design flow: a case study on G.729A for voice over internet protocol (VoIP) (MR, BG, DG), pp. 72–75.
DAC-2008-SparksWBLCPHR #industrial #what: Election year: what the electronics industry needs---and can expect---from the incoming administration (TS, PW, LB, RL, TC, CP, VH, CR), pp. 76–77.
DAC-2008-LinLLKWTCC: A 242mW, 10mm21080p H.264/AVC high profile encoder chip (YKL, DWL, CCL, TYK, SJW, WCT, WCC, TSC), pp. 78–83.
DAC-2008-ChoLKC #design #power management: The design of a low power carbon nanotube chemical sensor system (TSC, KJL, JK, APC), pp. 84–89.
DAC-2008-ChengLLCC #image #named #visual notation: iVisual: an intelligent visual sensor SoC with 2790fps CMOS image sensor and 205GOPS/W vision processor (CCC, CHL, CTL, SCC, LGC), pp. 90–95.
DAC-2008-KimKKLY #framework #mobile #platform #recognition: Vision platform for mobile intelligent robot based on 81.6 GOPS object recognition processor (DK, KK, JYK, SL, HJY), pp. 96–101.
DAC-2008-PinckneyBDMJNHSP #implementation: A MIPS R2000 implementation (NRP, TB, MD, MM, NJ, CN, DMH, JS, BP), pp. 102–107.
DAC-2008-KulkarniKPR #array #process: Process variation tolerant SRAM array for ultra low voltage applications (JPK, KK, SPP, KR), pp. 108–113.
DAC-2008-CheeKMPSBSRWS #energy #named: PicoCube: a 1 cm3 sensor node powered by harvested energy (YHC, MK, MM, NP, MS, FB, DS, JMR, PKW, SS), pp. 114–119.
DAC-2008-ChaudhuriGFHD #configuration management #embedded #runtime: An 8x8 run-time reconfigurable FPGA embedded in a SoC (SC, SG, FF, PH, JLD), pp. 120–125.
DAC-2008-SapatnekarHKDKMPS #manycore: Reinventing EDA with manycore processors (SSS, EH, KK, AD, DK, SM, DP, TS), pp. 126–127.
DAC-2008-HaritanHYPWNWM #challenge #design #exclamation #manycore #question #what: Multicore design is the challenge! what is the solution? (EH, TH, HY, PGP, WW, AN, DW, MM), pp. 128–130.
DAC-2008-Moon #composition #optimisation #verification: Compositional verification of retiming and sequential optimizations (IHM), pp. 131–136.
DAC-2008-GanaiG #scalability #slicing #towards: Tunneling and slicing: towards scalable BMC (MKG, AG), pp. 137–142.
DAC-2008-ChenXY #abstraction #automation #evaluation #optimisation #refinement: Optimizing automatic abstraction refinement for generalized symbolic trajectory evaluation (YC, FX, JY), pp. 143–148.
DAC-2008-DargaSM #performance #symmetry #using: Faster symmetry discovery using sparsity of symmetries (PTD, KAS, ILM), pp. 149–154.
DAC-2008-SenguptaS #design: Application-driven floorplan-aware voltage island design (DS, RAS), pp. 155–160.
DAC-2008-YanC #named: DeFer: deferred decision making enabled fixed-outline floorplanner (JZY, CC), pp. 161–166.
DAC-2008-JiangSC #design #scalability: Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs (ZWJ, BYS, YWC), pp. 167–172.
DAC-2008-XuC #multi: Broadcast electrode-addressing for pin-constrained multi-functional digital microfluidic biochips (TX, KC), pp. 173–178.
DAC-2008-CaoFHS #algorithm #multi #scalability: Optimality and improvement of dynamic voltage scaling algorithms for multimedia applications (ZC, BF, LH, MvdS), pp. 179–184.
DAC-2008-SridharanGM #embedded #power management #realtime: Feedback-controlled reliability-aware power management for real-time embedded systems (RS, NG, RNM), pp. 185–190.
DAC-2008-GoraczkoLLMPZ #clustering #embedded #energy #multi: Energy-optimal software partitioning in heterogeneous multiprocessor embedded systems (MG, JL, DL, SM, BP, FZ), pp. 191–196.
DAC-2008-LuSHWX #effectiveness #multi #optimisation: Customizing computation accelerators for extensible multi-issue processors with effective optimization techniques (YSL, LS, LH, ZW, NX), pp. 197–200.
DAC-2008-BaertGB #automation #case study #memory management: An automatic scratch pad memory management tool and MPEG-4 encoder case study (RB, EdG, EB), pp. 201–204.
DAC-2008-Abu-RahmaCWCYA #estimation #statistics: A methodology for statistical estimation of read access yield in SRAMs (MHAR, KC, JW, ZC, SSY, MA), pp. 205–210.
DAC-2008-LongM #automation #design #pipes and filters #self: Automated design of self-adjusting pipelines (JL, SOM), pp. 211–216.
DAC-2008-BastaniKWC #learning #predict #set: Speedpath prediction based on learning from a small set of examples (PB, KK, LCW, EC), pp. 217–222.
DAC-2008-WangLZTYTCN #scheduling: Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays (YW, WSL, XZ, JT, CY, JT, WC, JN), pp. 223–226.
DAC-2008-GoelV #analysis #modelling #standard #statistics: Statistical waveform and current source based standard cell models for accurate timing analysis (AG, SBKV), pp. 227–230.
DAC-2008-Cummings #design #verification: SystemVerilog implicit port enhancements accelerate system design & verification (CEC), pp. 231–236.
DAC-2008-Larson: Translation of an existing VMM-based SystemVerilog testbench to OVM (KDL), p. 237.
DAC-2008-DongLY #manycore #named #parallel #simulation: WavePipe: parallel transient simulation of analog and digital circuits on multi-core shared-memory machines (WD, PL, XY), pp. 238–243.
DAC-2008-GinsburgC #energy #parallel: The mixed signal optimum energy point: voltage and parallelism (BPG, APC), pp. 244–249.
DAC-2008-KshirsagarEB #analysis #performance: Analysis and implications of parasitic and screening effects on the high-frequency/RF performance of tunneling-carbon nanotube FETs (CK, MNEZ, KB), pp. 250–255.
DAC-2008-TurumellaS #concurrent #thread #verification: Assertion-based verification of a 32 thread SPARCTM CMT microprocessor (BT, MS), pp. 256–261.
DAC-2008-GuzeyWLF #analysis #functional #testing: Functional test selection based on unsupervised support vector analysis (OG, LCW, JRL, HF), pp. 262–267.
DAC-2008-HoTDDGS #identification #logic #verification: Early formal verification of conditional coverage points to identify intrinsically hard-to-verify logic (RCH, MT, MMD, ROD, JG, DES), pp. 268–271.
DAC-2008-ChoudhuryYGM: Technology exploration for graphene nanoribbon FETs (MRC, YY, JG, KM), pp. 272–277.
DAC-2008-LiASR #array #design #memory management #modelling #probability #random #statistics: Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement (JL, CA, SSS, KR), pp. 278–283.
DAC-2008-YuhSYC #algorithm: A progressive-ILP based routing algorithm for cross-referencing biochips (PHY, SSS, CLY, YWC), pp. 284–289.
DAC-2008-SchnerrBVR #embedded #simulation: High-performance timing simulation of embedded software (JS, OB, AV, WR), pp. 290–295.
DAC-2008-MohalikRDRSPJ #analysis #embedded #latency #model checking #realtime: Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts (SM, ACR, MGD, SR, PVS, PKP, SJ), pp. 296–299.
DAC-2008-SuhendraM #clustering #multi #predict: Exploring locking & partitioning for predictable shared caches on multi-cores (VS, TM), pp. 300–303.
DAC-2008-BournoutianO #design #embedded #reduction: Miss reduction in embedded processors through dynamic, power-friendly cache design (GB, AO), pp. 304–309.
DAC-2008-YagiRKHTMSDM #question: ESL hand-off: fact or EDA fiction? (HY, WR, TK, EH, HT, MM, GS, ND, GM), pp. 310–312.
DAC-2008-HerbertM #multi #variability: Characterizing chip-multiprocessor variability-tolerance (SH, DM), pp. 313–318.
DAC-2008-LiangM #analysis #execution #modelling #probability: Cache modeling in probabilistic execution time analysis (YL, TM), pp. 319–324.
DAC-2008-GaoKKLAM #estimation #hybrid #multi #performance #simulation #using: Multiprocessor performance estimation using hybrid simulation (LG, KK, SK, RL, GA, HM), pp. 325–330.
DAC-2008-HsuPB #data flow #graph #parallel #simulation #thread: Multithreaded simulation for synchronous dataflow graphs (CJH, JLP, SSB), pp. 331–336.
DAC-2008-BrockmanLKKM #array #design #memory management #multi #programmable #using: Design of a mask-programmable memory/multiplier array using G4-FET technology (JBB, SL, PMK, AK, MMM), pp. 337–338.
DAC-2008-JamaaALM #logic #programmable: Programmable logic circuits based on ambipolar CNFET (MHBJ, DA, YL, GDM), pp. 339–340.
DAC-2008-KimCK #parallel: Analog parallelism in ring-based VCOs (DDK, CC, JK), pp. 341–342.
DAC-2008-FaviC #communication: Techniques for fully integrated intra-/inter-chip optical communication (CF, EC), pp. 343–344.
DAC-2008-LiBNPC #approach #how #implementation #power management #set: How to let instruction set processor beat ASIC for low power wireless baseband implementation: a system level approach (ML, BB, DN, LVdP, FC), pp. 345–346.
DAC-2008-GuptaK #bound: Bounded-lifetime integrated circuits (PG, ABK), pp. 347–348.
DAC-2008-NarasimhanPB: Collective computing based on swarm intelligence (SN, SP, SB), pp. 349–350.
DAC-2008-PotkonjakK #behaviour: (Bio)-behavioral CAD (MP, FK), pp. 351–352.
DAC-2008-ReyKRCVKT #challenge #generative #multi #question: Next generation wireless-multimedia devices: who is up for the challenge? (JCR, AK, JMR, CC, TV, IK, TBT), pp. 353–354.
DAC-2008-BastaniCWA #statistics: Statistical diagnosis of unmodeled systematic timing effects (PB, NC, LCW, MSA), pp. 355–360.
DAC-2008-YuB #fault #multi #using: Multiple defect diagnosis using no assumptions on failing pattern characteristics (XY, RD(B), pp. 361–366.
DAC-2008-TamPB #analysis #automation #layout #locality #precise #using: Precise failure localization using automated layout analysis of diagnosis candidates (WCT, OP, RD(B), pp. 367–372.
DAC-2008-ParkM #analysis #debugging #locality #named: IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors (SBP, SM), pp. 373–378.
DAC-2008-GorjiaraG #architecture #automation #refinement: Automatic architecture refinement techniques for customizing processing elements (BG, DG), pp. 379–384.
DAC-2008-MilderFHP #implementation #representation: Formal datapath representation and manipulation for implementing DSP transforms (PAM, FF, JCH, MP), pp. 385–390.
DAC-2008-AhmadiZ #analysis #approach #hardware #optimisation: Symbolic noise analysis approach to computational hardware optimization (AA, MZ), pp. 391–396.
DAC-2008-PangR #fixpoint #optimisation: Optimizing imprecise fixed-point arithmetic circuits specified by Taylor Series through arithmetic transform (YP, KR), pp. 397–402.
DAC-2008-HeloueN #analysis #modelling: Parameterized timing analysis with general delay models and arbitrary variation sources (KRH, FNN), pp. 403–408.
DAC-2008-YanZTCM #distributed #linear #named #network #order #reduction: DeMOR: decentralized model order reduction of linear networks with massive ports (BY, LZ, SXDT, JC, BM), pp. 409–414.
DAC-2008-MoselhyD #equation #performance #probability: Stochastic integral equation solver for efficient variation-aware interconnect extraction (TM, LD), pp. 415–420.
DAC-2008-HanSE #3d #equation #modelling: Electric field integral equation combined with cylindrical conduction mode basis functions for electrical modeling of three-dimensional interconnects (KJH, MS, EE), pp. 421–424.
DAC-2008-FeldmannASSBG #analysis #modelling #multi: Driver waveform computation for timing analysis with multiple voltage threshold driver models (PF, SA, DS, GS, RB, HG), pp. 425–428.
DAC-2008-MoussaBJ #flexibility #multi #network: Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder (HM, AB, MJ), pp. 429–434.
DAC-2008-BalkanQV #hybrid #network #parallel: An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing (AOB, GQ, UV), pp. 435–440.
DAC-2008-ZhangGT #2d #algorithm #configuration management #fault tolerance: A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip (ZZ, AG, ST), pp. 441–446.
DAC-2008-KwonYHMCE #approach #memory management #parallel: A practical approach of memory access parallelization to exploit multiple off-chip DDR memories (WCK, SY, SMH, BM, KMC, SKE), pp. 447–452.
DAC-2008-FeldmannA #approach #modelling #physics #towards: Towards a more physical approach to gate modeling for timing, noise, and power (PF, SA), pp. 453–455.
DAC-2008-RajaVBG #analysis #modelling #performance: Transistor level gate modeling for accurate and fast timing, noise, and power analysis (SR, FV, MRB, JG), pp. 456–461.
DAC-2008-MenezesKA #grid #power management #verification: A “true” electrical cell model for timing, noise, and power grid verification (NM, CVK, CSA), pp. 462–467.
DAC-2008-KellerTK #challenge #modelling: Challenges in gate level modeling for delay and SI at 65nm and below (IK, KHT, VK), pp. 468–473.
DAC-2008-Trihy #challenge #library: Addressing library creation challenges from recent Liberty extensions (RT), pp. 474–479.
DAC-2008-SauerGL #framework #functional #modelling #named #performance #using: SystemClick: a domain-specific framework for early exploration using functional performance models (CS, MG, HPL), pp. 480–485.
DAC-2008-LeeJCHKKK #power management: Applying passive RFID system to wireless headphones for extreme low power consumption (JGL, DJ, JC, SH, JKK, JK, SWK), pp. 486–491.
DAC-2008-SenNSC #adaptation #named #power management #process: Pro-VIZOR: process tunable virtually zero margin low power adaptive RF for wireless systems (SS, VN, RS, AC), pp. 492–497.
DAC-2008-NieuwoudtKM #automation #configuration management #design #network: Automated design of tunable impedance matching networks for reconfigurable wireless applications (AN, JK, YM), pp. 498–503.
DAC-2008-ChoYBP #named #performance #predict: ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction (MC, KY, YB, DZP), pp. 504–509.
DAC-2008-ChenLC #predict: Predictive formulae for OPC with applications to lithography-friendly routing (TCC, GWL, YWC), pp. 510–515.
DAC-2008-JeongKPY #power management #reduction: Dose map and placement co-optimization for timing yield enhancement and leakage power reduction (KJ, ABK, CHP, HY), pp. 516–521.
DAC-2008-TehHT #framework #integration: Design-process integration for performance-based OPC framework (SHT, CHH, AT), pp. 522–527.
DAC-2008-WangZ #algorithm #incremental #performance: An efficient incremental algorithm for min-area retiming (JW, HZ), pp. 528–533.
DAC-2008-HurstMB #constraints #scalability: Scalable min-register retiming under timing and initializability constraints (APH, AM, RKB), pp. 534–539.
DAC-2008-CaseKMB: Merging nodes under sequential observability (MLC, VNK, AM, RKB), pp. 540–545.
DAC-2008-AlkabaniK #design: N-variant IC design: methodology and applications (YA, FK), pp. 546–551.
DAC-2008-KuehlmannBCRMN #verification: Verifying really complex systems: on earth and beyond (AK, AB, DEC, RAR, RMM, AN), pp. 552–553.
DAC-2008-DongWSXLC #3d #architecture #evaluation #memory management #ram: Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement (XD, XW, GS, YX, HHL, YC), pp. 554–559.
DAC-2008-BharathES #algorithm #automation #search-based #using: Automatic package and board decoupling capacitor placement using genetic algorithms and M-FDM (KB, EE, MS), pp. 560–565.
DAC-2008-LiuCJHZDH: Topological routing to maximize routability for package substrate (SL, GC, TTJ, LH, TZ, RD, XH), pp. 566–569.
DAC-2008-ZhangYZDKDKC #optimisation #power management #using: Low power passive equalizer optimization using tritonic step response (LZ, WY, HZ, AD, GAK, DMD, ESK, CKC), pp. 570–573.
DAC-2008-NikolovTSPPBZD #composition #design #multi #named #towards: Daedalus: toward composable multimedia MP-SoC design (HN, MT, TS, ADP, SP, RB, CZ, EFD), pp. 574–579.
DAC-2008-HaubeltSKM #agile #automation #behaviour #design #modelling #named #prototype: SystemCoDesigner: automatic design space exploration and rapid prototyping from behavioral models (CH, TS, JK, MM), pp. 580–585.
DAC-2008-GerstlauerPSGNAN #implementation #specification: Specify-explore-refine (SER): from specification to implementation (AG, JP, DS, DG, AN, DA, YN), pp. 586–591.
DAC-2008-SavolainenR #design #interface #mobile #performance #standard: Standard interfaces in mobile terminals: increasing the efficiency of device design and accelerating innovation (RS, TR), p. 592.
DAC-2008-NowakCCR #design: Holistic pathfinding: virtual wireless chip design for advanced technology and design exploration (MN, JC, CC, RR), p. 593.
DAC-2008-LiZY #analysis #verification: Full-chip leakage analysis in nano-scale technologies: mechanisms, variation sources, and verification (TL, WZ, ZY), pp. 594–599.
DAC-2008-PaikS #multi #optimisation #standard: Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements (SP, YS), pp. 600–605.
DAC-2008-AlkabaniMKP #variability: Input vector control for post-silicon leakage current minimization in the presence of manufacturing variability (YA, TM, FK, MP), pp. 606–609.
DAC-2008-NiM #power management #reduction #scheduling: Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction (MN, SOM), pp. 610–613.
DAC-2008-OgrasMM #adaptation #feedback #multi: Variation-adaptive feedback control for networks-on-chip with multiple clock domains (ÜYO, RM, DM), pp. 614–619.
DAC-2008-ChenLSK #multi: Application mapping for chip multiprocessors (GC, FL, SWS, MTK), pp. 620–625.
DAC-2008-LukasiewyczGHTRL #concurrent #integration #network #optimisation: Concurrent topology and routing optimization in automotive network integration (ML, MG, CH, JT, RR, BL), pp. 626–629.
DAC-2008-LaiWGLD #architecture: A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers (McL, ZW, LG, HL, KD), pp. 630–633.
DAC-2008-PuriVEWFYK #problem #question: Keeping hot chips cool: are IC thermal problems hot air? (RP, DV, DE, AJW, PDF, AY, SVK), pp. 634–635.
DAC-2008-LeeJH #satisfiability #scalability: Bi-decomposing large Boolean functions via interpolation and satisfiability solving (RRL, JHRJ, WLH), pp. 636–641.
DAC-2008-Abdollahi: Signature based Boolean matching in the presence of don’t cares (AA), pp. 642–647.
DAC-2008-QianR #logic #polynomial #probability #robust #synthesis: The synthesis of robust polynomial arithmetic with stochastic logic (WQ, MDR), pp. 648–653.
DAC-2008-Hurst #automation #logic #synthesis: Automatic synthesis of clock gating logic with controlled netlist perturbation (APH), pp. 654–657.
DAC-2008-FraerKM #paradigm #synthesis: A new paradigm for synthesis and propagation of clock gating conditions (RF, GK, MKM), pp. 658–663.
DAC-2008-Vucurevich #3d: 3-D semiconductor’s: more from Moore (TV), p. 664.
DAC-2008-Bautista #challenge: Tera-scale computing and interconnect challenges (JB), pp. 665–667.
DAC-2008-FranzonDSLOTMLDBSO #3d #design: Design and CAD for 3D integrated circuits (PDF, WRD, MBS, SL, ECO, TT, SM, SL, TD, SB, BS, KO), pp. 668–673.
DAC-2008-Haensch #3d #integration #question #why: Why should we do 3D integration? (WH), pp. 674–675.
DAC-2008-VeetilSB #analysis #incremental #monte carlo #performance #statistics: Efficient Monte Carlo based incremental statistical timing analysis (VV, DS, DB), pp. 676–681.
DAC-2008-YeZP #analysis #equation #linear #multi: Generalized Krylov recycling methods for solution of multiple related linear equation systems in electromagnetic analysis (ZY, ZZ, JRP), pp. 682–687.
DAC-2008-KumarKS #analysis #framework: A framework for block-based timing sensitivity analysis (SVK, CVK, SSS), pp. 688–693.
DAC-2008-LiuTCC #correlation #modelling #statistics: Accurate and analytical statistical spatial correlation modeling for VLSI DFM applications (JHL, MFT, LC, CCPC), pp. 694–697.
DAC-2008-ImaiSNM #analysis #framework #parametricity #statistics: Non-parametric statistical static timing analysis: an SSTA framework for arbitrary distribution (MI, TS, NN, KM), pp. 698–701.
DAC-2008-ChenCP #framework: An integrated nonlinear placement framework with congestion and porosity aware buffer planning (TCC, AC, DZP), pp. 702–707.
DAC-2008-JiangS #algorithm #scalability: Circuit-wise buffer insertion and gate sizing algorithm with scalability (ZJ, WS), pp. 708–713.
DAC-2008-ChangHHLWL: Type-matching clock tree for zero skew clock gating (CMC, SHH, YKH, JZL, HPW, YSL), pp. 714–719.
DAC-2008-RajaramP #design #robust #synthesis: Robust chip-level clock tree synthesis for SOC designs (AR, DZP), pp. 720–723.
DAC-2008-MoffittPLA #optimisation: Path smoothing via discrete optimization (MDM, DAP, ZL, CJA), pp. 724–727.
DAC-2008-JungRP #manycore #modelling #probability: Stochastic modeling of a thermally-managed multi-core system (HJ, PR, MP), pp. 728–733.
DAC-2008-YeoLK #manycore #predict: Predictive dynamic thermal management for multicore systems (IY, CCL, EJK), pp. 734–739.
DAC-2008-GuC #3d #game studies #interactive: Control theory-based DVS for interactive 3D games (YG, SC), pp. 740–745.
DAC-2008-HuangSSRS #design #manycore #perspective: Many-core design from a thermal perspective (WH, MRS, KS, RJR, KS), pp. 746–749.
DAC-2008-ZhouYP #compilation #reduction: Compiler-driven register re-assignment for register file power-density and temperature reduction (XZ, CY, PP), pp. 750–753.
DAC-2008-CengCSSLAMIK #framework #named #parallel: MAPS: an integrated framework for MPSoC application parallelization (JC, JC, WS, HS, RL, GA, HM, TI, HK), pp. 754–759.
DAC-2008-FaruqueKH #communication #distributed #named #runtime: ADAM: run-time agent-based distributed application mapping for on-chip communication (MAAF, RK, JH), pp. 760–765.
DAC-2008-YuP #communication #embedded #latency #multi #performance: Latency and bandwidth efficient communication through system customization for embedded multiprocessors (CY, PP), pp. 766–771.
DAC-2008-TarjanBS #named: Federation: repurposing scalar cores for out-of-order instruction issue (DT, MB, KS), pp. 772–775.
DAC-2008-ChangWSC #algorithm #energy #multi #named: ETAHM: an energy-aware task allocation algorithm for heterogeneous multiprocessor (PCC, IWW, JJJS, CPC), pp. 776–779.
DAC-2008-DavisTYZ #configuration management #hardware #satisfiability: A practical reconfigurable hardware accelerator for Boolean satisfiability solvers (JDD, ZT, FY, LZ), pp. 780–785.
DAC-2008-PaulB #configuration management #memory management #performance #resource management #using: Reconfigurable computing using content addressable memory for improved performance and resource usage (SP, SB), pp. 786–791.
DAC-2008-KuonR #architecture #automation: Automated transistor sizing for FPGA architecture exploration (IK, JR), pp. 792–795.
DAC-2008-BijanskyA #named: TuneFPGA: post-silicon tuning of dual-Vdd FPGAs (SB, AA), pp. 796–799.
DAC-2008-Mitra #verification: Strategies for mainstream usage of formal verification (RSM), pp. 800–805.
DAC-2008-Beers #experience #verification: Pre-RTL formal verification: an intel experience (RB), pp. 806–811.
DAC-2008-Ng #challenge #modelling #using #verification: Challenges in using system-level models for RTL verification (KN), pp. 812–815.
DAC-2008-UrardMGC #equivalence: Leveraging sequential equivalence checking to enable system-level to RTL flows (PU, AM, RG, NC), pp. 816–821.
DAC-2008-GulatiK #fault #simulation #towards #using: Towards acceleration of fault simulation using graphics processing units (KG, SPK), pp. 822–827.
DAC-2008-ElmWIZLM #clustering #reduction: Scan chain clustering for test power reduction (ME, HJW, MEI, CGZ, JL, NM), pp. 828–833.
DAC-2008-HuangYX #composition #on the #reliability #testing: On reliable modular testing with vulnerable test access mechanisms (LH, FY, QX), pp. 834–839.
DAC-2008-ReddyPL #detection #on the #testing: On tests to detect via opens in digital CMOS circuits (SMR, IP, CL), pp. 840–845.
DAC-2008-RoyKM #hardware: Protecting bus-based hardware IP by secret sharing (JAR, FK, ILM), pp. 846–851.
DAC-2008-PiyachonL #automaton #design #finite #pattern matching #performance: Design of high performance pattern matching engine through compact deterministic finite automata (PP, YL), pp. 852–857.
DAC-2008-PatelP #design #hardware #named #reliability #security: SHIELD: a software hardware design methodology for security and reliability of MPSoCs (KP, SP), pp. 858–861.
DAC-2008-LinSH #multi #realtime: A multi-resolution AHB bus tracer for real-time compression of forward/backward traces in a circular buffer (YTL, WCS, IJH), pp. 862–865.
DAC-2008-HsiehH #debugging #embedded #framework #interface #platform: An embedded infrastructure of debug and trace interface for the DSP platform (MCH, CTH), pp. 866–871.
DAC-2008-MandalBMM #design #named #towards: IntellBatt: towards smarter battery design (SKM, PB, SPM, RNM), pp. 872–877.
DAC-2008-LiuMZM #architecture: A power and temperature aware DRAM architecture (SL, SOM, YZ, GM), pp. 878–883.
DAC-2008-KurimotoSAYOTS #detection #fault #optimisation #scalability: Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scaling (MK, HS, RA, TY, HO, HT, HS), pp. 884–889.
DAC-2008-CoskunRG #learning #multi #online #using: Temperature management in multiprocessor SoCs using online learning (AKC, TSR, KCG), pp. 890–893.
DAC-2008-DasikaDFMB #using: DVFS in loop accelerators using BLADES (GSD, SD, KF, SAM, DMB), pp. 894–897.
DAC-2008-ReyNKKAHCS #question: DFM in practice: hit or hype? (JCR, NSN, ABK, FK, RA, CH, LC, VS), pp. 898–899.
DAC-2008-YeLNC #modelling #simulation #statistics: Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness (YY, FL, SRN, YC), pp. 900–905.
DAC-2008-El-MoselhyEW #algorithm #parametricity #performance #scalability #set: Efficient algorithm for the computation of on-chip capacitance sensitivities with respect to a large set of parameters (TAEM, IME, DW), pp. 906–911.
DAC-2008-JoshiCSBA #power management #reduction #using: Leakage power reduction using stress-enhanced layouts (VJ, BC, DS, DB, KA), pp. 912–917.
DAC-2008-GargNK #design #performance: A fast, analytical estimator for the SEU-induced pulse width in combinational designs (RG, CN, SPK), pp. 918–923.
DAC-2008-KrishnaswamyMH #design #logic #on the #reliability: On the role of timing masking in reliable logic circuit design (SK, ILM, JPH), pp. 924–929.
DAC-2008-MaestroR #reliability: Study of the effects of MBUs on the reliability of a 150 nm SRAM device (JAM, PR), pp. 930–935.
DAC-2008-KunduGG #design #partial order #reduction #scalability #testing: Partial order reduction for scalable testing of systemC TLM designs (SK, MKG, RG), pp. 936–941.
DAC-2008-HaldarSPDG #c++ #modelling #verification: Construction of concrete verification models from C++ (MH, GS, SP, BD, AG), pp. 942–947.
DAC-2008-SenOA #multi #predict #runtime #verification: Predictive runtime verification of multi-processor SoCs in SystemC (AS, VO, MSA), pp. 948–953.
DAC-2008-HamersE #automation #identification #independence: Automated hardware-independent scenario identification (JH, LE), pp. 954–959.
DAC-2008-CookS #design #predict #using: Predictive design space exploration using genetically programmed response surfaces (HC, KS), pp. 960–965.
DAC-2008-OzisikyilmazMC #design #machine learning #performance #using: Efficient system design space exploration using machine learning techniques (BÖ, GM, ANC), pp. 966–969.
DAC-2008-JinC #benchmark #case study #metric #performance #simulation #statistics #using: Improve simulation efficiency using statistical benchmark subsetting: an ImplantBench case study (ZJ, ACC), pp. 970–973.
DAC-2008-GandikotaBS #analysis #modelling #statistics: Modeling crosstalk in statistical static timing analysis (RG, DB, DS), pp. 974–979.
DAC-2008-JiangM #power management #reduction #scheduling: Power gating scheduling for power/ground noise reduction (HJ, MMS), pp. 980–985.
DAC-2008-DuanZK #design: Forbidden transition free crosstalk avoidance CODEC design (CD, CZ, SPK), pp. 986–991.
DAC-2008-PuriJBGLM #synthesis: Custom is from Venus and synthesis from Mars (RP, WHJ, SB, TG, JL, RKM), p. 992.

Limor FixProceedings of the 45th Design Automation ConferenceDAC, 2008.

Contents (195 items)

Limor Fix
Proceedings of the 45th Design Automation Conference
DAC, 2008.