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Travelled to:
2 × USA
Collaborated with:
K.Tseng I.Keller K.H.Tam
Talks about:
nois (2) challeng (1) analysi (1) window (1) static (1) model (1) level (1) delay (1) below (1) gate (1)

Person: Vinod Kariat

DBLP DBLP: Kariat:Vinod

Contributed to:

DAC 20082008
DAC 20032003

Wrote 2 papers:

DAC-2008-KellerTK #challenge #modelling
Challenges in gate level modeling for delay and SI at 65nm and below (IK, KHT, VK), pp. 468–473.
DAC-2003-TsengK #analysis
Static noise analysis with noise windows (KT, VK), pp. 864–868.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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