BibSLEIGH — Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture

Fazal Hameed, Lars Bauer, Jörg Henkel
Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture
DAC, 2014.

DAC 2014

@inproceedings{DAC-2014-HameedBH,
	author        = "Fazal Hameed and Lars Bauer and Jörg Henkel",
	booktitle     = "{Proceedings of the 51st Annual Design Automation Conference}",
	doi           = "10.1145/2593069.2593197",
	isbn          = "978-1-4503-2730-5",
	pages         = "6",
	publisher     = "{ACM}",
	title         = "{Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture}",
	year          = 2014,
}

Fazal Hameed, Lars Bauer, Jörg HenkelReducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache ArchitectureDAC, 2014.

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Fazal Hameed, Lars Bauer, Jörg Henkel
Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture
DAC, 2014.