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Travelled to:
15 × USA
5 × Germany
8 × France
Collaborated with:
M.Shafique L.Bauer S.Rehman S.Parameswaran T.Bonny H.Lekatsas M.A.A.Faruque N.Iqbal M.U.K.Khan W.Wolf F.Kriebel F.Hameed Z.Wang S.Bampi B.Zatt J.Jahn H.Javaid S.Pagani D.Sun H.Khdr T.Lv M.A.Siddique W.Ahmed S.Kobbe J.Chen H.Bokhari P.V.Aceituno C.Hsieh N.Cheung T.Ebi F.Sampaio V.Jakkula S.Garg Y.Li R.Ernst D.Gnad H.Amrouch S.T.Chakradhar H.Zhang L.V.Agostini B.Vogel A.Grudnitsky M.A.Siddique B.Molkenthin R.Krist R.Marculescu M.Pedram T.Lee T.Givargis F.Vahid T.Li J.A.Ambrose W.Ahmad R.Hafiz A.O.Tüfek S.Iqtedar O.Hasan F.Samie D.Marculescu A.K.Singh A.Kumar M.Grellert S.Kreutz S.Kramer A.Janapsatya A.Ignjatovic J.Chan J.Becker C.M.Diniz F.V.Dalcin D.Palomino A.A.Susin J.M.Borrmann F.L.Walter J.Xu M.Sankaradass X.Zhang J.Peddersen M.A.Kochte M.E.Imhof H.Wunderlich R.König T.Stripf N.Dutt P.Gupta S.R.Nassif M.B.Tahoori N.Wehn S.Radhakrishnan R.G.Ragel J.Heisswolf A.Zaib A.Zwinkau A.Weichslgartner J.Teich G.Snelting A.Herkersdorf
Talks about:
adapt (20) system (19) video (17) code (16) effici (15) core (15) chip (15) architectur (14) instruct (13) softwar (12)

Person: Jörg Henkel

DBLP DBLP: Henkel:J=ouml=rg

Contributed to:

DAC 20152015
DATE 20152015
DAC 20142014
DATE 20142014
DAC 20132013
DATE 20132013
DAC 20122012
DATE 20122012
DAC 20112011
DATE 20112011
DATE 20102010
DAC 20092009
DATE 20092009
DAC 20082008
DATE 20082008
DAC 20072007
DATE 20072007
DATE v2 20042004
DAC 20032003
DATE 20032003
DAC 20022002
DATE 20022002
DAC 20012001
DAC 20002000
DATE 20002000
DAC 19991999
DAC 19981998
DAC 19971997

Wrote 92 papers:

DAC-2015-BokhariJSHP #architecture #manycore #named
SuperNet: multimode interconnect architecture for manycore chips (HB, HJ, MS, JH, SP), p. 6.
DAC-2015-GnadSKRSH #named #variability
Hayat: harnessing dark silicon and variability for aging deceleration and balancing (DG, MS, FK, SR, DS, JH), p. 6.
DAC-2015-HenkelKPS #roadmap
New trends in dark silicon (JH, HK, SP, MS), p. 6.
DAC-2015-KhdrPSH #resource management
Thermal constrained resource management for mixed ILP-TLP workloads in dark silicon chips (HK, SP, MS, JH), p. 6.
DAC-2015-ShafiqueAHH #configuration management #latency
A low latency generic accuracy configurable adder (MS, WA, RH, JH), p. 6.
DAC-2015-ShafiqueKTH #anti #energy #named #video
EnAAM: energy-efficient anti-aging for on-chip video memories (MS, MUKK, AOT, JH), p. 6.
DATE-2015-BokhariJSHP #adaptation
Malleable NoC: dark silicon inspired adaptable Network-on-Chip (HB, HJ, MS, JH, SP), pp. 1245–1248.
DATE-2015-DinizSDBH #architecture #hardware #performance #standard #video
A deblocking filter hardware architecture for the high efficiency video coding standard (CMD, MS, FVD, SB, JH), pp. 1509–1514.
DATE-2015-IqtedarHSH #analysis #distributed #probability
Formal probabilistic analysis of distributed dynamic thermal management (SI, OH, MS, JH), pp. 1221–1224.
DATE-2015-KhanSH #adaptation #manycore #power management
Power-efficient accelerator allocation in adaptive dark silicon many-core systems (MUKK, MS, JH), pp. 916–919.
DATE-2015-KobbeBH #adaptation #modelling #on the fly #performance
Adaptive on-the-fly application performance modeling for many cores (SK, LB, JH), pp. 730–735.
DATE-2015-KriebelRSASH #analysis #combinator #configuration management #fault #named #performance
ACSEM: accuracy-configurable fast soft error masking analysis in combinatorial circuits (FK, SR, DS, PVA, MS, JH), pp. 824–829.
DATE-2015-PaganiCSH #modelling #named #performance
MatEx: efficient transient and peak temperature computation for compact thermal models (SP, JJC, MS, JH), pp. 1515–1520.
DATE-2015-SamieBHH #multi #online
Online binding of applications to multiple clock domains in shared FPGA-based systems (FS, LB, CMH, JH), pp. 25–30.
DATE-2015-ShafiqueGGH #manycore #variability
Variability-aware dark silicon management in on-chip many-core systems (MS, DG, SG, JH), pp. 387–392.
DATE-2015-ZhangJSPHP #hardware #manycore #named #pipes and filters
E-pipeline: elastic hardware/software pipelines on a many-core fabric (XZ, HJ, MS, JP, JH, SP), pp. 363–368.
DAC-2014-BokhariJSHP #design #energy #multi #named
darkNoC: Designing Energy-Efficient Network-on-Chip with Multi-Vt Cells for Dark Silicon (HB, HJ, MS, JH, SP), p. 6.
DAC-2014-HameedBH #architecture #latency #novel
Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture (FH, LB, JH), p. 6.
DAC-2014-HeisswolfZZKWTHSHB #communication #named #programming
CAP: Communication Aware Programming (JH, AZ, AZ, SK, AW, JT, JH, GS, AH, JB), p. 6.
DAC-2014-HenkelBZRS #architecture #dependence #multi
Multi-Layer Dependability: From Microarchitecture to Application Level (JH, LB, HZ, SR, MS), p. 6.
DAC-2014-KriebelRSSH #adaptation #fault #named
ASER: Adaptive Soft Error Resilience for Reliability-Heterogeneous Processors in the Dark Silicon Era (FK, SR, DS, MS, JH), p. 6.
DAC-2014-RehmanKSSH #adaptation #code generation #dependence #named #process #reliability
dTune: Leveraging Reliable Code Generation for Adaptive Dependability Tuning under Process Variation and Aging-Induced Effects (SR, FK, DS, MS, JH), p. 6.
DAC-2014-ShafiqueGHM #challenge #reliability #variability
The EDA Challenges in the Dark Silicon Era: Temperature, Reliability, and Variability Perspectives (MS, SG, JH, DM), p. 6.
DAC-2014-ZhangKIBWH #configuration management #named #reliability
GUARD: GUAranteed Reliability in Dynamically Reconfigurable Systems (HZ, MAK, MEI, LB, HJW, JH), p. 6.
DATE-2014-KhanSH #architecture #manycore #performance #power management #video
Software architecture of High Efficiency Video Coding for many-core systems with power-efficient workload balancing (MUKK, MS, JH), pp. 1–6.
DATE-2014-KhdrESAH #multi #named
mDTM: Multi-objective dynamic thermal management for on-chip systems (HK, TE, MS, HA, JH), pp. 1–6.
DATE-2014-PalominoSASH #named #performance #video
hevcDTM: Application-driven Dynamic Thermal Management for High Efficiency Video Coding (DP, MS, HA, AAS, JH), pp. 1–4.
DATE-2014-RehmanKSH #compilation #reliability
Compiler-driven dynamic reliability management for on-chip systems under variabilities (SR, FK, MS, JH), pp. 1–4.
DATE-2014-SampaioSZBH #architecture #distributed #energy #memory management #named #performance #video
dSVM: Energy-efficient distributed Scratchpad Video Memory Architecture for the next-generation High Efficiency Video Coding (FS, MS, BZ, SB, JH), pp. 1–6.
DAC-2013-HenkelBDGNSTW #lessons learnt #reliability #roadmap
Reliable on-chip systems in the nano-era: lessons learnt and future trends (JH, LB, ND, PG, SRN, MS, MBT, NW), p. 10.
DAC-2013-JahnPKCH #configuration management #optimisation #pipes and filters
Optimizations for configuring and mapping software pipelines in many core systems (JJ, SP, SK, JJC, JH), p. 8.
DAC-2013-LiSARHP #adaptation #embedded #fault #named #runtime
RASTER: runtime adaptive spatial/temporal error resiliency for embedded processors (TL, MS, JAA, SR, JH, SP), p. 7.
DAC-2013-ShafiqueRAH #fault #optimisation #reliability
Exploiting program-level masking and error propagation for constrained reliability optimization (MS, SR, PVA, JH), p. 9.
DAC-2013-SinghSKH #manycore #overview #roadmap
Mapping on multi/many-core systems: survey of current and emerging trends (AKS, MS, AK, JH), p. 10.
DATE-2013-HameedBH #adaptation #multi
Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores (FH, LB, JH), pp. 77–82.
DATE-2013-HsiehWH #configuration management #distributed #named #network
DANCE: distributed application-aware node configuration engine in shared reconfigurable sensor networks (CMH, ZW, JH), pp. 839–842.
DATE-2013-JahnH #architecture #manycore #named #pipes and filters #self
Pipelets: self-organizing software pipelines for many-core architectures (JJ, JH), pp. 1516–1521.
DATE-2013-KhanBBSH #video
An H.264 Quad-FullHD low-latency intra video encoder (MUKK, JMB, LB, MS, JH), pp. 115–120.
DATE-2013-KhanSGH #collaboration #complexity #reduction
Hardware-software collaborative complexity reduction scheme for the emerging HEVC intra encoder (MUKK, MS, MG, JH), pp. 125–128.
DATE-2013-LiSRRRAHP #configuration management #named
CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors (TL, MS, SR, SR, RGR, JAA, JH, SP), pp. 707–712.
DATE-2013-RehmanSAKCH #hardware #reliability
Leveraging variable function resilience for selective software reliability on unreliable hardware (SR, MS, PVA, FK, JJC, JH), pp. 1759–1764.
DATE-2013-SampaioZSABH #energy #estimation #memory management #multi #video
Energy-efficient memory hierarchy for motion and disparity estimation in multiview video coding (FS, BZ, MS, LVA, SB, JH), pp. 665–670.
DATE-2013-ShafiqueVH #adaptation #hybrid #manycore #power management #self
Self-adaptive hybrid dynamic power management for many-core systems (MS, BV, JH), pp. 51–56.
DATE-2013-WangH #embedded #modelling #performance #simulation
Fast and accurate cache modeling in source-level simulation of embedded software (ZW, JH), pp. 587–592.
DAC-2012-RehmanSH #compilation #scheduling
Instruction scheduling for reliability-aware compilation (SR, MS, JH), pp. 1292–1300.
DAC-2012-ShafiqueZWBH #adaptation #memory management #multi #power management #video
Adaptive power management of on-chip video memory for multiview video coding (MS, BZ, FLW, SB, JH), pp. 866–875.
DATE-2012-GrudnitskyBH #architecture #configuration management
Partial online-synthesis for mixed-grained reconfigurable architectures (AG, LB, JH), pp. 1555–1560.
DATE-2012-HameedBH #adaptation #architecture #manycore #runtime
Dynamic cache management in multi-core architectures through run-time adaptation (FH, LB, JH), pp. 485–490.
DATE-2012-ShafiqueZRKH #adaptation #power management
Power-efficient error-resiliency for H.264/AVC Context-Adaptive Variable Length Coding (MS, BZ, SR, FK, JH), pp. 697–702.
DATE-2012-WangH #compilation #embedded #optimisation #simulation
Accurate source-level simulation of embedded software with respect to compiler optimizations (ZW, JH), pp. 382–387.
DAC-2011-IqbalSH #dependence #fault #monte carlo #named #power management #probability #scheduling
SEAL: soft error aware low power scheduling by Monte Carlo state space under the influence of stochastic spatial and temporal dependencies (NI, MAS, JH), pp. 134–139.
DAC-2011-JavaidSPH #adaptation #case study #multi #pipes and filters #power management #video
Low-power adaptive pipelined MPSoCs for multimedia: an H.264 video encoder case study (HJ, MS, SP, JH), pp. 1032–1037.
DAC-2011-ZattSSABH #adaptation #energy #estimation #multi #runtime #video
Run-time adaptive energy-aware motion and disparity estimation in multiview video coding (BZ, MS, FS, LVA, SB, JH), pp. 1026–1031.
DATE-2011-AhmedSBH #configuration management #multi #named #runtime
mRTS: Run-time system for reconfigurable processors with multi-grained instruction-set extensions (WA, MS, LB, JH), pp. 1554–1559.
DATE-2011-HameedFH #3d #adaptation #architecture #manycore #runtime
Dynamic thermal management in 3D multi-core architecture through run-time adaptation (FH, MAAF, JH), pp. 299–304.
DATE-2011-JahnFH #adaptation #architecture #migration #multi #named #runtime
CARAT: Context-aware runtime adaptive task migration for multi core architectures (JJ, MAAF, JH), pp. 515–520.
DATE-2011-ShafiqueBAH #configuration management #manycore #resource management #runtime
Minority-Game-based resource allocation for run-time reconfigurable multi-core processors (MS, LB, WA, JH), pp. 1261–1266.
DATE-2011-ZattSBH #architecture #estimation #hardware #parallel #pipes and filters #throughput #video
Multi-level pipelined parallel hardware architecture for high throughput motion and disparity estimation in Multiview Video Coding (BZ, MS, SB, JH), pp. 1448–1453.
DATE-2010-IqbalSH #estimation #execution #named #order #pipes and filters #recursion
RMOT: Recursion in model order for task execution time estimation in a software pipeline (NI, MAS, JH), pp. 953–956.
DATE-2010-IqbalSH10a #estimation #execution #graph #monte carlo #named
DAGS: Distribution agnostic sequential Monte Carlo scheme for task execution time estimation (NI, MAS, JH), pp. 1645–1648.
DATE-2010-KoenigBSSABH #architecture #configuration management #multi #named #novel
KAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array architecture (RK, LB, TS, MS, WA, JB, JH), pp. 819–824.
DATE-2010-ShafiqueBH #adaptation #energy #estimation #named #predict #runtime #video
enBudget: A Run-Time Adaptive Predictive Energy-Budgeting scheme for energy-aware Motion Estimation in H.264/MPEG-4 AVC video encoder (MS, LB, JH), pp. 1725–1730.
DATE-2010-ShafiqueMH #adaptation #complexity #reduction #using #video
An HVS-based Adaptive Computational Complexity Reduction Scheme for H.264/AVC video encoder using Prognostic Early Mode Exclusion (MS, BM, JH), pp. 1713–1718.
DAC-2009-BonnyH #named #performance
LICT: left-uncompressed instructions compression technique to improve the decoding performance of VLIW processors (TB, JH), pp. 903–906.
DATE-2009-BauerSH #architecture #configuration management #design
Cross-architectural design space exploration tool for reconfigurable processors (LB, MS, JH), pp. 958–963.
DATE-2009-FaruqueEH #adaptation #communication #configuration management #runtime
Configurable links for runtime adaptive on-chip communication (MAAF, TE, JH), pp. 256–261.
DATE-2009-IqbalH #performance
Efficient constant-time entropy decoding for H.264 (NI, JH), pp. 1440–1445.
DATE-2009-ShafiqueBH #approach #design #hardware #parallel #performance #predict #video
A parallel approach for high performance hardware design of intra prediction in H.264/AVC Video Codec (MS, LB, JH), pp. 1434–1439.
DAC-2008-BauerSH #embedded #runtime #set
Run-time instruction set selection in a transmutable embedded processor (LB, MS, JH), pp. 56–61.
DAC-2008-FaruqueKH #communication #distributed #named #runtime
ADAM: run-time agent-based distributed application mapping for on-chip communication (MAAF, RK, JH), pp. 760–765.
DATE-2008-BauerSKH #embedded #runtime #set
Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set (LB, MS, SK, JH), pp. 752–757.
DATE-2008-BonnyH #embedded #encoding
Instruction Re-encoding Facilitating Dense Embedded Code (TB, JH), pp. 770–775.
DATE-2008-FaruqueH #architecture #communication
Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures (MAAF, JH), pp. 1238–1243.
DAC-2007-BauerSKH #framework #named #platform #set
RISPP: Rotating Instruction Set Processing Platform (LB, MS, SK, JH), pp. 791–796.
DAC-2007-BonnyH #performance
Instruction Splitting for Efficient Code Compression (TB, JH), pp. 646–651.
DATE-2007-BonnyH #performance
Efficient code density through look-up table compression (TB, JH), pp. 809–814.
DATE-2007-JanapsatyaIPH #agile #simulation
Instruction trace compression for rapid instruction cache simulation (AJ, AI, SP, JH), pp. 803–808.
DATE-v2-2004-CheungPHC #equivalence #named #using
MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor (NC, SP, JH, JC), pp. 1020–1027.
DATE-v2-2004-MarculescuPH #design #distributed #multi #perspective
Distributed Multimedia System Design: A Holistic Perspective (RM, MP, JH), pp. 1342–1349.
DATE-v2-2004-XuWHCL #case study #design #embedded #video
A Case Study in Networks-on-Chip Design for Embedded Video (JX, WW, JH, STC, TL), pp. 770–777.
DAC-2003-LekatsasHCJS #agile #framework #hardware #named #platform #prototype
CoCo: a hardware/software platform for rapid prototyping of code compression technologies (HL, JH, STC, VJ, MS), pp. 306–311.
DATE-2003-CheungHP #agile #case study
Rapid Configuration and Instruction Selection for an ASIP: A Case Study (NC, JH, SP), pp. 10802–10809.
DATE-2003-LvHLW #encoding
Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address Buses (TL, JH, HL, WW), pp. 10542–10549.
DAC-2002-LekatsasHJ #design #embedded #hardware #performance
Design of an one-cycle decompression hardware for performance increase in embedded systems (HL, JH, VJ), pp. 34–39.
DATE-2002-LeeWH #design #implementation #multi #platform #runtime
Dynamic Runtime Re-Scheduling Allowing Multiple Implementations of a Task for Platform-Based Designs (TML, WW, JH), pp. 296–301.
DATE-2002-LvWHL #adaptation #encoding #taxonomy
An Adaptive Dictionary Encoding Scheme for SOC Data Buses (TL, WW, JH, HL), pp. 1059–1064.
DAC-2001-HenkelL #adaptation #design #named #power management
A2BC: Adaptive Address Bus Coding for Low Power Deep Sub-Micron Designs (JH, HL), pp. 744–749.
DAC-2000-LekatsasHW #design #embedded #power management
Code compression for low power embedded system design (HL, JH, WW), pp. 294–299.
DATE-2000-HenkeGV #design #estimation #performance
Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design (JH, TG, FV), pp. 333–338.
DAC-1999-Henkel #approach #clustering #embedded #hardware #power management
A Low Power Hardware/Software Partitioning Approach for Core-Based Embedded Systems (JH), pp. 122–127.
DAC-1998-LiH #embedded #energy #estimation #framework
A Framework for Estimation and Minimizing Energy Dissipation of Embedded HW/SW Systems (YL, JH), pp. 188–193.
DAC-1997-HenkelE #hardware #using
A Hardware/Software Partitioner Using a Dynamically Determined Granularity (JH, RE), pp. 691–696.

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