Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
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Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
DATE, 2005.

DATE 2005
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@inproceedings{DATE-2005-AmoryLMM,
	author        = "Alexandre M. Amory and Marcelo Lubaszewski and Fernando Gehm Moraes and Edson I. Moreno",
	booktitle     = "{Proceedings of the Ninth Conference on Design, Automation and Test in Europe}",
	doi           = "10.1109/DATE.2005.304",
	isbn          = "0-7695-2288-2",
	pages         = "62--63",
	publisher     = "{IEEE Computer Society}",
	title         = "{Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture}",
	year          = 2005,
}

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