Hierarchical Variance Analysis for Analog Circuits Based on Graph Modelling and Correlation Loop Tracing
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Fang Liu, Jacob J. Flomenberg, Devaka V. Yasaratne, Sule Ozev
Hierarchical Variance Analysis for Analog Circuits Based on Graph Modelling and Correlation Loop Tracing
DATE, 2005.

DATE 2005
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@inproceedings{DATE-2005-LiuFYO,
	author        = "Fang Liu and Jacob J. Flomenberg and Devaka V. Yasaratne and Sule Ozev",
	booktitle     = "{Proceedings of the Ninth Conference on Design, Automation and Test in Europe}",
	doi           = "10.1109/DATE.2005.175",
	isbn          = "0-7695-2288-2",
	pages         = "126--131",
	publisher     = "{IEEE Computer Society}",
	title         = "{Hierarchical Variance Analysis for Analog Circuits Based on Graph Modelling and Correlation Loop Tracing}",
	year          = 2005,
}

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