`Travelled to:`

1 × USA

3 × Germany

4 × France

`Collaborated with:`

E.Yilmaz O.Sinanoglu A.Nassery E.S.Erdogan F.Liu C.K.H.Suresh J.R.Carter D.J.Sorin I.Bayraktaroglu A.Orailoglu D.Chang R.Karri G.Shofner L.Winemberg J.J.Flomenberg D.V.Yasaratne A.Sehgal K.Chakrabarty O.E.Erol R.A.Parekhji L.Balasubramanian J.W.Jeong S.Sen V.Natarajan M.Slamani L.Deng V.Kundur N.S.J.Naga M.K.Ozel B.Bakkaloglu S.Kiaei D.Pratab T.Dar

`Talks about:`

circuit (6) test (5) analog (4) character (3) analysi (3) signal (3) loop (3) mix (3) model (2) adapt (2)

## Person: Sule Ozev

### DBLP: Ozev:Sule

### Contributed to:

### Wrote 13 papers:

- DATE-2015-ErolOSPB #metric #using
- On-chip measurement of bandgap reference voltage using a small form factor VCO based zoom-in ADC (OEE, SO, CKHS, RAP, LB), pp. 1559–1562.
- DATE-2014-ChangOSK #approximate #estimation #statistics
- Approximating the age of RF/analog circuits through re-characterization and statistical estimation (DC, SO, OS, RK), pp. 1–4.
- DATE-2014-JeongOSNS #parametricity #self
- Built-in self-test and characterization of polar transmitter parameters in the loop-back mode (JWJ, SO, SS, VN, MS), pp. 1–6.
- DATE-2013-DengKNOYOBKPD
- Electrical calibration of spring-mass MEMS capacitive accelerometers (LD, VK, NSJN, MKO, EY, SO, BB, SK, DP, TD), pp. 571–574.
- DATE-2013-SureshYOS #adaptation #multi #reduction
- Adaptive reduction of the frequency search space for multi-vdd digital circuits (CKHS, EY, SO, OS), pp. 292–295.
- DATE-2013-YilmazSWO #analysis #fault #industrial #scalability #simulation
- Fault analysis and simulation of large scale industrial mixed-signal circuits (EY, GS, LW, SO), pp. 565–570.
- DATE-2012-NasseryO
- An analytical technique for characterization of transceiver IQ imbalances in the loop-back mode (AN, SO), pp. 1084–1089.
- DAC-2009-YilmazO #adaptation
- Adaptive test elimination for analog/RF circuits (EY, SO), pp. 720–725.
- DATE-2007-ErdoganO #analysis #using
- An ADC-BiST scheme using sequential code analysis (ESE, SO), pp. 713–718.
- DATE-2005-CarterOS #concurrent #fault #modelling #testing
- Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown (JRC, SO, DJS), pp. 300–305.
- DATE-2005-LiuFYO #analysis #correlation #graph #modelling
- Hierarchical Variance Analysis for Analog Circuits Based on Graph Modelling and Correlation Loop Tracing (FL, JJF, DVY, SO), pp. 126–131.
- DATE-2005-SehgalLOC #testing
- Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores (AS, FL, SO, KC), pp. 50–55.
- DATE-2000-OzevBO #synthesis
- Test Synthesis for Mixed-Signal SOC Paths (SO, IB, AO), pp. 128–133.