A high performance SEU-tolerant latch for nanoscale CMOS technology
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Zhengfeng Huang
A high performance SEU-tolerant latch for nanoscale CMOS technology
DATE, 2014.

DATE 2014
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@inproceedings{DATE-2014-Huang,
	author        = "Zhengfeng Huang",
	booktitle     = "{Proceedings of the 18th Conference and Exhibition on Design, Automation and Test in Europe}",
	doi           = "10.7873/DATE.2014.175",
	pages         = "1--5",
	publisher     = "{IEEE}",
	title         = "{A high performance SEU-tolerant latch for nanoscale CMOS technology}",
	year          = 2014,
}

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