BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Used together with:
design (5)
voltag (4)
cmos (4)
reliabl (3)
sram (3)

Stem nanoscal$ (all stems)

21 papers:

DATEDATE-2014-EbrahimiETSCA #analysis #embedded #fault
Comprehensive analysis of alpha and neutron particle-induced soft errors in an embedded processor at nanoscales (ME, AE, MBT, RS, EC, DA), pp. 1–6.
DATEDATE-2014-Huang #performance
A high performance SEU-tolerant latch for nanoscale CMOS technology (ZH), pp. 1–5.
DATEDATE-2013-De #design
Near-threshold voltage design in nanoscale CMOS (VD), p. 612.
DATEDATE-2012-AbellanPABBMB #clustering #communication #design #framework
Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs (JLA, JFP, MEA, DB, DB, AM, LB), pp. 491–496.
DACDAC-2011-SorgenfreiS #detection #using
Single-molecule electronic detection using nanoscale field-effect devices (SS, KLS), pp. 712–717.
Dynamic write limited minimum operating voltage for nanoscale SRAMs (SN, VC, RCA, BHC), pp. 467–472.
Bayesian virtual probe: minimizing variation characterization cost for nanoscale IC technologies via Bayesian inference (WZ, XL, RAR), pp. 262–267.
DATEDATE-2010-ChandraPA #on the
On the efficacy of write-assist techniques in low voltage nanoscale SRAMs (VC, CP, RCA), pp. 345–350.
ASPLOSASPLOS-2010-IpekCNBM #memory management #reliability
Dynamically replicated memory: building reliable systems from nanoscale resistive memories (EI, JC, EBN, DB, TM), pp. 3–14.
Nanoscale digital computation through percolation (MA, MDR, CN), pp. 615–616.
DACDAC-2009-DrmanacLW #predict #process #variability
Predicting variability in nanoscale lithography processes (DGD, FL, LCW), pp. 545–550.
DATEDATE-2009-ChandraA #reliability #scalability
Impact of voltage scaling on nanoscale SRAM reliability (VC, RCA), pp. 387–392.
DATEDATE-2009-LudoviciVMRGLGB #constraints #design
Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints (DL, FGV, SM, CGR, MEG, PL, GNG, DB), pp. 562–565.
ASPLOSASPLOS-2009-PistolDL #architecture
Architectural implications of nanoscale integrated sensing and computing (CP, CD, ARL), pp. 13–24.
DACDAC-2006-AnanthanR #physics #process
A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS (HA, KR), pp. 413–418.
DACDAC-2006-RadT #clustering #hybrid
A new hybrid FPGA with nanoscale clusters and CMOS routing (RMR, MT), pp. 727–730.
DATEDATE-2006-MohantyVK #optimisation
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits (SPM, RV, EK), pp. 1191–1196.
DATEDATE-2006-PaulKKAR #design #estimation #performance #reliability
Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits (BCP, KK, HK, MAA, KR), pp. 780–785.
ASPLOSASPLOS-2006-PatwardhanJDL #architecture #fault #self
A defect tolerant self-organizing nanoscale SIMD architecture (JPP, VJ, CD, ARL), pp. 241–251.
DATEDATE-2005-Marculescu #bound #design #energy #fault tolerance
Energy Bounds for Fault-Tolerant Nanoscale Designs (DM), pp. 74–79.
DATEDATE-2002-Man #complexity #integration #on the
On Nanoscale Integration and Gigascale Complexity in the Post.Com World (HDM), p. 12.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.