26 papers:
DAC-2014-HeldS #optimisation- Post-Routing Latch Optimization for Timing Closure (SH, US), p. 6.
DATE-2014-Huang #performance- A high performance SEU-tolerant latch for nanoscale CMOS technology (ZH), pp. 1–5.
- DATE-2014-KimKKYL #design
- Coarse-grained Bubble Razor to exploit the potential of two-phase transparent latch designs (HK, DK, JJK, SY, SL), pp. 1–6.
- DATE-2013-LuZ #constraints #fault
- Retiming for Soft Error Minimization Under Error-Latching Window Constraints (YL, HZ), pp. 1008–1013.
SIGMOD-2013-Horikawa #data type #design #evaluation #implementation- Latch-free data structures for DBMS: design, implementation, and evaluation (TH), pp. 409–420.
VLDB-2011-PandisTJA #named- PLP: Page Latch-free Shared-everything OLTP (IP, PT, RJ, AA), pp. 610–621.
- VLDB-2011-SewallCKSD #architecture #manycore #named #parallel
- PALM: Parallel Architecture-Friendly Latch-Free Modifications to B+ Trees on Many-Core Processors (JS, JC, CK, NS, PD), pp. 795–806.
- DAC-2010-ChuangKSC #optimisation
- Pulsed-latch aware placement for timing-integrity optimization (YLC, SK, YS, YWC), pp. 280–285.
- DATE-2009-PaikSS #named #performance #synthesis
- HLS-l: High-level synthesis of high performance latch-based circuits (SP, IS, YS), pp. 1112–1117.
- DATE-2008-ShiRWP #analysis #modelling #statistics
- Latch Modeling for Statistical Timing Analysis (SXS, AR, DW, DZP), pp. 1136–1141.
- DAC-2007-ChelceaVG #self
- Self-Resetting Latches for Asynchronous Micro-Pipelines (TC, GV, SCG), pp. 986–989.
- DAC-2007-SrivastavaR #equation
- Interdependent Latch Setup/Hold Time Characterization via Euler-Newton Curve Tracing on State-Transition Equations (SS, JSR), pp. 136–141.
- DATE-2007-SrivastavaR #agile
- Rapid and accurate latch characterization via direct Newton solution of setup/hold times (SS, JSR), pp. 1006–1011.
SIGAda-2006-MarkowRB- Catch that speeding turtle: latching onto fun graphics in CS1 (TM, EKR, JRSB), pp. 29–34.
- DAC-2003-NgPMJ #industrial #problem
- Solving the latch mapping problem in an industrial setting (KN, MRP, RM, JJ), pp. 442–447.
- DATE-2003-Zhou #verification
- Timing Verification with Crosstalk for Transparently Latched Circuits (HZ), pp. 10056–10061.
- DAC-2001-SinghMM #latency
- Latency and Latch Count Minimization in Wave Steered Circuits (AS, AM, MMS), pp. 383–388.
- DATE-2000-NicoliciA #clustering #multi #power management
- Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits (NN, BMAH), pp. 715–722.
- DATE-2000-NooshabadiMNSS
- A Single Phase Latch for High Speed GaAs Domino Circuits (SN, JAMN, AN, RS, JS), p. 760.
- DAC-1997-SentovichTB #optimisation #performance #set #using
- Efficient Latch Optimization Using Exclusive Sets (ES, HT, GB), pp. 8–11.
- DAC-1992-LinLE
- Analyzing Cycle Stealing on Synchronous Circuits with Level-Sensitive Latches (IL, JAL, KE), pp. 393–398.
- VLDB-1992-GottemukkalaL #database
- Locking and Latching in a Memory-Resident Database System (VG, TJL), pp. 533–544.
- DAC-1991-ChandraFGP #novel
- ATPG Based on a Novel Grid-Addressable Latch Element (SJC, TF, TG, KP), pp. 282–286.
- DAC-1990-SakallahMO #analysis #design
- Analysis and Design of Latch-Controlled Synchronous Digital Circuits (KAS, TNM, KO), pp. 111–117.
- VLDB-1990-Mohan90a #commit #named #novel #transaction
- Commit_LSN: A Novel and Simple Method for Reducing Locking and Latching in Transaction Processing Systems (CM), pp. 406–418.
- DAC-1981-AlmyR #fault #using
- Using error latch trace to obtain diagnostic information (PMA, JLR), pp. 355–359.
