A Method for Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability
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J. Akita, K. Asada
A Method for Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability
DATE, 1994.

EDAC 1994
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@inproceedings{EDAC-1994-AkitaA,
	author        = "J. Akita and K. Asada",
	booktitle     = "{Proceedings of the European Conference on Design Automation (EDAC), European Test Conference (ETC) and the European Event in ASIC Design (EUROASIC)}",
	isbn          = "0-8186-5410-4",
	pages         = "420--424",
	publisher     = "{IEEE Computer Society}",
	title         = "{A Method for Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability}",
	year          = 1994,
}

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