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Travelled to:
1 × France
1 × Ireland
1 × Singapore
1 × USA
1 × United Kingdom
3 × Italy
Collaborated with:
A.Podelski M.Heizmann B.Westphal A.Nutz B.Musa D.Beyer M.Dangl S.F.Arenis J.Hoenicke E.Ermis V.Langenfeld M.M.Mohamed J.Christ M.Lindenmann C.Schilling A.Stahlbauer J.Leike M.Muñiz A.S.Andisha S.Wissert
Talks about:
contribut (5) competit (5) ultim (5) verif (4) softwar (3) check (3) autom (3) standard (2) interpol (2) industri (2)

Person: Daniel Dietsch

DBLP DBLP: Dietsch:Daniel

Contributed to:

CAV 20152015
ESEC/FSE 20152015
TACAS 20152015
FM 20142014
TACAS 20142014
TACAS 20132013
FM 20112011
RE 20112011
FSE 20162016
ESEC/FSE 20172017

Wrote 12 papers:

CAV-2015-DietschHLP #approach #ltl #model checking #modulo theories
Fairness Modulo Theory: A New Approach to LTL Software Model Checking (DD, MH, VL, AP), pp. 49–66.
ESEC-FSE-2015-0001DDHS #validation #verification
Witness validation and stepwise testification across software verifiers (DB, MD, DD, MH, AS), pp. 721–733.
TACAS-2015-HeizmannDLMP #array #contest
Ultimate Automizer with Array Interpolation — (Competition Contribution) (MH, DD, JL, BM, AP), pp. 455–457.
TACAS-2015-NutzDMP #contest #memory management #safety
ULTIMATE KOJAK with Memory Safety Checks — (Competition Contribution) (AN, DD, MMM, AP), pp. 458–460.
FM-2014-ArenisWDMA #consistency #industrial #standard #verification
The Wireless Fire Alarm System: Ensuring Conformance to Industrial Standards through Formal Verification (SFA, BW, DD, MM, ASA), pp. 658–672.
TACAS-2014-ErmisNDHP #contest
Ultimate Kojak — (Competition Contribution) (EE, AN, DD, JH, AP), pp. 421–423.
TACAS-2014-HeizmannCDHLMSWP #contest #satisfiability
Ultimate Automizer with Unsatisfiable Cores — (Competition Contribution) (MH, JC, DD, JH, ML, BM, CS, SW, AP), pp. 418–420.
TACAS-2013-HeizmannCDEHLNSP #contest
Ultimate Automizer with SMTInterpol — (Competition Contribution) (MH, JC, DD, EE, JH, ML, AN, CS, AP), pp. 641–643.
FM-2011-DietschWP #verification
System Verification through Program Verification (DD, BW, AP), pp. 27–41.
RE-2011-DietschAWP #ambiguity #formal method #industrial #standard #visual notation
Disambiguation of industrial standards through formalization and graphical languages (DD, SFA, BW, AP), pp. 265–270.
FSE-2016-BeyerDDH #correctness #verification
Correctness witnesses: exchanging verification results between verifiers (DB, MD, DD, MH), pp. 326–337.
ESEC-FSE-2017-DietschHMNP #model checking
Craig vs. Newton in software model checking (DD, MH, BM, AN, AP), pp. 487–497.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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