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Travelled to:
1 × Germany
1 × Italy
Collaborated with:
S.P.Fekete J.Teich G.Baier T.Erlebach A.Hall H.Schilling M.Skutella
Talks about:
constraint (1) placement (1) tempor (1) preced (1) length (1) optim (1) modul (1) bound (1) fpga (1) flow (1)

Person: Ekkehard Köhler

DBLP DBLP: K=ouml=hler:Ekkehard

Contributed to:

ICALP (1) 20062006
DATE 20012001

Wrote 2 papers:

ICALP-v1-2006-BaierEHKSS #bound
Length-Bounded Cuts and Flows (GB, TE, AH, EK, HS, MS), pp. 679–690.
DATE-2001-FeketeKT #constraints #precedence
Optimal FPGA module placement with temporal precedence constraints (SPF, EK, JT), pp. 658–667.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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