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Travelled to:
1 × USA
Collaborated with:
J.A.Walter J.Leenstra B.Leppla H.Münster K.W.Kark B.Wile
Talks about:
multiprocessor (1) hierarch (1) approach (1) random (1) verif (1) simul (1) cmos (1)

Person: Gerhard Döttling

DBLP DBLP: D=ouml=ttling:Gerhard

Contributed to:

DAC 19971997

Wrote 1 papers:

DAC-1997-WalterLDLMKW #approach #multi #random #simulation #verification
Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors (JAW, JL, GD, BL, HJM, KWK, BW), pp. 89–94.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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