Travelled to:1 × Germany
3 × USA
Collaborated with:N.Mäding H.Wunderlich M.E.Imhof C.G.Zoellin M.Elm J.Pille R.Sautter S.Büttner S.Ehrenreich W.Haller J.A.Walter G.Döttling B.Leppla H.Münster K.W.Kark B.Wile V.Raman G.K.Attaluri R.Barber N.Chainani D.Kalmuk V.KulandaiSamy S.Lightstone S.Liu G.M.Lohman T.Malkemus R.Müller I.Pandis B.Schiefer D.Sharpe R.Sidle A.J.Storm L.Zhang
Talks about:processor (2) reduct (2) power (2) test (2) scan (2) multiprocessor (1) architectur (1) synergist (1) hierarch (1) approach (1)
Person: Jens Leenstra
DBLP: Leenstra:Jens
Contributed to:
2013
20082007
20061997Wrote 5 papers:
- VLDB-2013-RamanABCKKLLLLMMPSSSSZ
- DB2 with BLU Acceleration: So Much More than Just a Column Store (VR, GKA, RB, NC, DK, VK, JL, SL, SL, GML, TM, RM, IP, BS, DS, RS, AJS, LZ), pp. 1080–1091.
- DAC-2008-ElmWIZLM #clustering #reduction
- Scan chain clustering for test power reduction (ME, HJW, MEI, CGZ, JL, NM), pp. 828–833.
- DAC-2007-ImhofZWML #reduction #testing
- Scan Test Planning for Power Reduction (MEI, CGZ, HJW, NM, JL), pp. 521–526.
- DATE-DF-2006-MadingLPSBEH #architecture #fixpoint
- The vector fixed point unit of the synergistic processor element of the cell architecture processor (NM, JL, JP, RS, SB, SE, WH), pp. 244–248.
- DAC-1997-WalterLDLMKW #approach #multi #random #simulation #verification
- Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors (JAW, JL, GD, BL, HJM, KWK, BW), pp. 89–94.