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Travelled to:
3 × USA
Collaborated with:
F.N.Najm I.N.Hajj C.W.Moon K.P.Belkhale P.Yang
Talks about:
maximum (2) current (2) circuit (2) estim (2) cmos (2) hierarch (1) extract (1) signal (1) resolv (1) reduct (1)

Person: Harish Kriplani

DBLP DBLP: Kriplani:Harish

Contributed to:

DAC 20022002
DAC 19931993
DAC 19921992

Wrote 3 papers:

DAC-2002-MoonKB #graph #reduction
Timing model extraction of hierarchical blocks by graph reduction (CWM, HK, KPB), pp. 152–157.
DAC-1993-KriplaniNYH #correlation
Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits (HK, FNN, PY, INH), pp. 384–388.
DAC-1992-KriplaniNH #estimation
Maximum Current Estimation in CMOS Circuits (HK, FNN, INH), pp. 2–7.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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