BibSLEIGH — Farid_N

Travelled to:

18 × USA
3 × France

Collaborated with:

∅ N.Azizi I.N.Hajj K.R.Heloue N.H.A.Ghani D.Kouroussis B.Wu J.Zhu S.Onaissi H.Kriplani Abhishek P.A.Haddad A.Goyal N.Menezes I.A.Ferzli S.Bodapati M.Nemani S.Gupta R.Panda M.Y.Zhang M.G.Xakellis P.Yang G.Nabaa R.Ahmadi V.Saxena S.Goel F.Taraporevala J.Liu M.M.Khellah V.De R.Burch D.E.Hocevar H.Mangassarian A.G.Veneris S.Safarpour M.S.Abadir

Talks about:

power (16) estim (14) circuit (12) grid (8) analysi (7) time (6) current (5) variat (5) verif (5) model (5)

Person: Farid N. Najm

DBLP: Najm:Farid_N=

Contributed to:

2012

2011

2009

2008

2007

2006

2005

2004

2003

2002

1998

1997

1995

1994

1993

1992

1991

1988

Wrote 33 papers:

DAC-2012-AbhishekN #grid #incremental #power management #verification: Incremental power grid verification (A, FNN), pp. 151–156.
DAC-2011-GhaniN #branch #grid #power management #using #verification: Power grid verification using node and branch dominance (NHAG, FNN), pp. 682–687.
DAC-2011-HaddadN #analysis #grid #power management #using: Power grid correction using sensitivity analysis under an RC model (PAH, FNN), pp. 688–693.
DAC-2011-OnaissiTLN #analysis #approach #performance: A fast approach for static timing analysis covering all PVT corners (SO, FT, JL, FNN), pp. 777–782.
DATE-2011-GoyalN #grid #performance #power management #using #verification: Efficient RC power grid verification using node elimination (AG, FNN), pp. 257–260.
DAC-2009-GhaniN #approximate #grid #performance #power management #using #verification: Fast vectorless power grid verification using an approximate inverse technique (NHAG, FNN), pp. 184–189.
DAC-2009-OnaissiHN #optimisation #process: Clock skew optimization via wiresizing for timing sign-off covering all process corners (SO, KRH, FNN), pp. 196–201.
DAC-2008-HeloueN #analysis #modelling: Parameterized timing analysis with general delay models and arbitrary variation sources (KRH, FNN), pp. 403–408.
DAC-2007-HeloueAN #correlation #estimation #modelling: Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation (KRH, NA, FNN), pp. 93–98.
DATE-2007-MangassarianVSNA #estimation #process #pseudo #satisfiability #using: Maximum circuit activity estimation using pseudo-boolean satisfiability (HM, AGV, SS, FNN, MSA), pp. 1538–1543.
DAC-2006-AziziN #product line: A family of cells to reduce the soft-error-rate in ternary-CAM (NA, FNN), pp. 779–784.
DAC-2006-NabaaAN #adaptation #architecture #process: An adaptive FPGA architecture with process variation compensation and reduced leakage (GN, NA, FNN), pp. 624–629.
DAC-2005-AziziKDN #design #power management #scalability: Variations-aware low-power design with voltage scaling (NA, MMK, VD, FNN), pp. 529–534.
DAC-2005-Najm #analysis #on the #statistics: On the need for statistical timing analysis (FNN), pp. 764–765.
DAC-2005-WuZN #approach #estimation #parametricity: A non-parametric approach for dynamic range estimation of nonlinear systems (BW, JZ, FNN), pp. 841–844.
DAC-2004-KouroussisAN #power management #worst-case: Worst-case circuit delay taking into account power supply variations (DK, RA, FNN), pp. 652–657.
DAC-2004-NajmM #analysis #statistics: Statistical timing analysis based on a timing yield model (FNN, NM), pp. 460–465.
DAC-2004-WuZN #approach #estimation: An analytical approach for dynamic range estimation (BW, JZ, FNN), pp. 472–477.
DAC-2003-FerzliN #estimation #grid #power management #process #statistics: Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations (IAF, FNN), pp. 856–859.
DAC-2003-KouroussisN #grid #independence #power management #verification: A static pattern-independent technique for power grid voltage integrity verification (DK, FNN), pp. 99–104.
DAC-2002-BodapatiN #analysis #megamodelling: High-level current macro-model for power-grid analysis (SB, FNN), pp. 385–390.
DAC-1998-NemaniN #estimation #perspective: Delay Estimation VLSI Circuits from a High-Level View (MN, FNN), pp. 591–594.
DAC-1997-GuptaN #estimation #megamodelling: Power Macromodeling for High Level Power Estimation (SG, FNN), pp. 365–370.
DAC-1997-PandaN #power management #synthesis: Technology-Dependent Transformations for Low-Power Synthesis (RP, FNN), pp. 650–655.
EDTC-1997-SaxenaNH #approach #estimation #monte carlo: Monte-Carlo approach for power estimation in sequential circuits (VS, FNN, INH), pp. 416–420.
DAC-1995-Najm #correlation #estimation #feedback: Feedback, Correlation, and Delay Concerns in the Power Estimation of VLSI Circuits (FNN), pp. 612–617.
DAC-1995-NajmGH #estimation: Power Estimation in Sequential Circuits (FNN, SG, INH), pp. 635–640.
DAC-1995-NajmZ #process #worst-case: Extreme Delay Sensitivity and the Worst-Case Switching Activity in VLSI Circuits (FNN, MYZ), pp. 623–627.
DAC-1994-XakellisN #estimation #process #statistics: Statistical Estimation of the Switching Activity in Digital Circuits (MGX, FNN), pp. 728–733.
DAC-1993-KriplaniNYH #correlation: Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits (HK, FNN, PY, INH), pp. 384–388.
DAC-1992-KriplaniNH #estimation: Maximum Current Estimation in CMOS Circuits (HK, FNN, INH), pp. 2–7.
DAC-1991-Najm #probability #process: Transition Density, A Stochastic Measure of Activity in Digital Circuits (FNN), pp. 644–649.
DAC-1988-BurchNYH #analysis #estimation #independence #reliability: Pattern-Independent Current Estimation for Reliability Analysis of CMOS Circuits (RB, FNN, PY, DEH), pp. 294–299.