BibSLEIGH corpus
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Open Knowledge
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Travelled to:
1 × France
1 × Germany
Collaborated with:
I.A.Maio F.G.Canavero S.Grivet-Talocia Z.Chen W.D.Becker G.A.Katopis
Talks about:
macromodel (2) digit (2) interconnect (1) system (1) combin (1) assess (1) simul (1) devic (1) port (1) fdtd (1)

Person: Igor S. Stievano

DBLP DBLP: Stievano:Igor_S=

Contributed to:

DATE 20032003
DATE 20022002

Wrote 2 papers:

DATE-2003-Grivet-TalociaSMC #megamodelling #simulation
Combined FDTD/Macromodel Simulation of Interconnected Digital Devices (SGT, ISS, IAM, FGC), pp. 10536–10541.
DATE-2002-StievanoCMCBK #assessment #megamodelling
Macromodeling of Digital I/O Ports for System EMC Assessment (ISS, FGC, IAM, ZC, WDB, GAK), pp. 1044–1048.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.