BibSLEIGH — macromodel stem

Used together with:

circuit (9)
analog (8)
digit (7)
level (7)
power (7)

Stem macromodel$ (all stems)

36 papers:

DATE-2014-UbolliGBC #linear #megamodelling: Sensitivity-based weighting for passivity enforcement of linear macromodels in power integrity applications (AU, SGT, MB, AC), pp. 1–6.
DATE-2011-GobbatoCG #megamodelling #parallel #scalability: A parallel Hamiltonian eigensolver for passivity characterization and enforcement of large interconnect macromodels (LG, AC, SGT), pp. 26–31.
DATE-2010-ChineaGDDK #megamodelling #on the #performance: On the construction of guaranteed passive macromodels for high-speed channels (AC, SGT, DD, TD, LK), pp. 1142–1147.
DATE-2010-PanYZS #approach #megamodelling #order #performance #reduction: An efficient transistor-level piecewise-linear macromodeling approach for model order reduction of nonlinear circuits (XP, FY, XZ, YS), pp. 1673–1676.
CAiSE-2009-SalayME #megamodelling #modelling #using: Using Macromodels to Manage Collections of Related Models (RS, JM, SME), pp. 141–155.
ASE-2008-SalayME #megamodelling #modelling: Managing Models through Macromodeling (RS, JM, SME), pp. 447–450.
DAC-2007-WangLP #design #megamodelling: Parameterized Macromodeling for Analog System-Level Design Exploration (JW, XL, LTP), pp. 940–943.
DAC-2007-WangLR #automation #megamodelling #named #parametricity #variability: PV-PPV: Parameter Variability Aware, Automatically Extracted, Nonlinear Time-Shifted Oscillator Macromodels (ZW, XL, JSR), pp. 142–147.
DAC-2006-LaiR #megamodelling #multi #performance #robust: A multilevel technique for robust and efficient extraction of phase macromodels of digitally controlled oscillators (XL, JSR), pp. 1017–1022.
DAC-2006-WeiD #composition #development #megamodelling: Systematic development of nonlinear analog circuit macromodels through successive operator composition and nonlinear model decoupling (YW, AD), pp. 1023–1028.
DAC-2006-ZhaoPSYF #algorithm #linear #megamodelling #performance #programming #using: A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming (MZ, RP, SS, SY, YF), pp. 217–222.
DAC-2005-DingV #megamodelling #performance: A combined feasibility and performance macromodel for analog circuits (MD, RV), pp. 63–68.
DAC-2005-DongR #automation #megamodelling #performance: Automated nonlinear Macromodelling of output buffers for high-speed digital applications (ND, JSR), pp. 51–56.
DAC-2005-TiwaryR #megamodelling #on-demand #scalability: Scalable trajectory methods for on-demand analog macromodel extraction (SKT, RAR), pp. 403–408.
DAC-2005-WeiD #behaviour #development #megamodelling: Systematic development of analog circuit structural macromodels through behavioral model decoupling (YW, AD), pp. 57–62.
DATE-2005-DingV #approach #megamodelling #modelling #performance: A Two-Level Modeling Approach to Analog Circuit Performance Macromodeling (MD, RV), pp. 1088–1089.
DAC-2004-MuttrejaRRJ #automation #embedded #energy #megamodelling #performance: Automated energy/performance macromodeling of embedded software (AM, AR, SR, NKJ), pp. 99–102.
DATE-v2-2004-ElviraMAG #generative #megamodelling #performance #simulation: A Macromodelling Methodology for Efficient High-Level Simulation of Substrate Noise Generation (LE, FM, XA, JLG), pp. 1362–1363.
DATE-v2-2004-WangMR #automation #megamodelling #predict: Automated, Accurate Macromodelling of Digital Aggressors for Power/Ground/Substrate Noise Prediction (ZW, RM, JSR), pp. 824–829.
DAC-2003-LiLXP #analysis #megamodelling: Analog and RF circuit macromodels for system-level analysis (XL, PL, YX, LTP), pp. 478–483.
DATE-2003-Grivet-TalociaSMC #megamodelling #simulation: Combined FDTD/Macromodel Simulation of Interconnected Digital Devices (SGT, ISS, IAM, FGC), pp. 10536–10541.
DATE-2003-XuLLP #megamodelling: Noise Macromodel for Radio Frequency Integrated Circuits (YX, XL, PL, LTP), pp. 10150–10155.
DAC-2002-CaoLCC #megamodelling #named #power management: HiPRIME: hierarchical and passivity reserved interconnect macromodeling engine for RLKC power delivery (YC, YML, THC, CCPC), pp. 379–384.
DAC-2002-LiuSRC #data mining #design #megamodelling #mining #scalability: Remembrance of circuits past: macromodeling by data mining in large analog design spaces (HL, AS, RAR, LRC), pp. 437–442.
DATE-2002-KhazakaN #megamodelling: Compact Macromodel for Lossy Coupled Transmission Lines (RK, MSN), p. 1114.
DATE-2002-StievanoCMCBK #assessment #megamodelling: Macromodeling of Digital I/O Ports for System EMC Assessment (ISS, FGC, IAM, ZC, WDB, GAK), pp. 1044–1048.
DAC-1998-ChenR #megamodelling: A Power Macromodeling Technique Based on Power Sensitivity (ZC, KR), pp. 678–683.
DAC-1998-DengiR #2d #bound #megamodelling: Boundary Element Method Macromodels for 2-D Hierachical Capacitance Extraction (EAD, RAR), pp. 218–223.
DAC-1997-ForzanFG #megamodelling #performance #standard: Accurate and Efficient Macromodel of Submicron Digital Standard Cells (CF, BF, CG), pp. 633–637.
DAC-1997-GuptaN #estimation #megamodelling: Power Macromodeling for High Level Power Estimation (SG, FNN), pp. 365–370.
DAC-1996-DartuTP #megamodelling #simulation: RC-Interconnect Macromodels for Timing Simulation (FD, BT, LTP), pp. 544–547.
DAC-1995-WempleY #analysis #megamodelling #using: Mixed-Signal Switching Noise Analysis Using Voronoi-Tessellated Substrate Macromodels (ILW, ATY), pp. 439–444.
DAC-1994-HaqueEC #megamodelling #multi #simulation: A New Time-Domain Macromodel for Transient Simulation of Uniform/Nonuniform Multiconductor Transmission-Line Interconnections (MH, AEZ, SC), pp. 628–633.
DAC-1985-Matson #megamodelling: Macromodeling of digital MOS VLSI Circuits (MDM), pp. 141–151.
DAC-1982-LightnerH #algorithm #functional #megamodelling #testing: Implication algorithms for MOS switch level functional macromodeling implication and testing (MRL, GDH), pp. 691–698.
DAC-1979-HsiehR #functional #latency #megamodelling: Macrosimulation with Quasi-general Symbolic FET Macromodel and Functional Latency (HYH, NBR), pp. 229–234.