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Travelled to:
13 × USA
3 × Germany
5 × France
Collaborated with:
S.Bhardwaj V.Hanumaiah M.Hamzeh A.Shrivastava A.Goel D.Blaauw C.Chakrabarti Q.Wang R.Rao P.Ghanta K.Chopra K.S.Chatha J.M.Wang N.Chang R.Panda A.Agarwal V.Zolotov Y.Cao S.Raj D.N.Rakhmatov S.Sirichotiyakul S.Ganguly Y.Lai M.Pedram F.Liu Y.Cho J.Zhuo S.Dasika R.Srinivasan K.Agarwal D.Sylvester S.R.Nassif W.Wang S.Yang R.Vattikonda P.Chen D.Kadetotad Z.Xu A.Mohanty B.Lin J.Ye J.Seo S.Yu
Talks about:
analysi (7) circuit (6) variat (6) power (6) optim (6) time (6) applic (5) map (5) base (4) awar (4)

Person: Sarma B. K. Vrudhula

DBLP DBLP: Vrudhula:Sarma_B=_K=

Contributed to:

DATE 20152015
DAC 20142014
DAC 20132013
DAC 20122012
DATE 20112011
DAC 20092009
DATE 20092009
DAC 20082008
DATE 20082008
DAC 20072007
DAC 20062006
DAC 20052005
DATE 20052005
DAC 20042004
DATE v2 20042004
DAC 20032003
DATE 20032003
DAC 20022002
DATE 19981998
DAC 19971997
DAC 19931993

Wrote 28 papers:

DATE-2015-ChenKXMLYVSCY #algorithm #array #learning
Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip (PYC, DK, ZX, AM, BL, JY, SBKV, JsS, YC, SY), pp. 854–859.
Branch-Aware Loop Mapping on CGRAs (MH, AS, SBKV), p. 6.
DAC-2013-HamzehSV #architecture #configuration management #named
REGIMap: register-aware application mapping on coarse-grained reconfigurable architectures (CGRAs) (MH, AS, SBKV), p. 10.
DAC-2012-HamzehSV #morphism #named #using
EPIMap: using epimorphism to map applications on CGRAs (MH, AS, SBKV), pp. 1284–1291.
DATE-2011-HanumaiahV #manycore #realtime
Reliability-aware thermal management for hard real-time applications on multi-core processors (VH, SBKV), pp. 137–142.
DAC-2009-HanumaiahRVC #constraints #manycore #throughput
Throughput optimal task allocation under thermal constraints for multi-core processors (VH, RR, SBKV, KSC), pp. 776–781.
DATE-2009-HanumaiahVC #constraints #manycore #performance
Performance optimal speed control of multi-core processors under thermal constraints (VH, SBKV, KSC), pp. 1548–1551.
DAC-2008-GoelV #analysis #modelling #standard #statistics
Statistical waveform and current source based standard cell models for accurate timing analysis (AG, SBKV), pp. 227–230.
DATE-2008-GoelV #analysis #standard
Current source based standard cell model for accurate signal integrity and timing analysis (AG, SBKV), pp. 574–579.
DAC-2007-WangYBVVLC #performance
The Impact of NBTI on the Performance of Combinational and Sequential Circuits (WW, SY, SB, RV, SBKV, FL, YC), pp. 364–369.
DAC-2006-BhardwajVGC #analysis #modelling #optimisation #process
Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits (SB, SBKV, PG, YC), pp. 791–796.
DAC-2006-ChoCCV #cost analysis #embedded #energy #power management
High-level power management of embedded systems with application-specific energy cost functions (YC, NC, CC, SBKV), pp. 568–573.
DAC-2006-GhantaVBP #analysis #correlation #power management #probability #scalability
Stochastic variational analysis of large power grids considering intra-die correlations (PG, SBKV, SB, RP), pp. 211–216.
DAC-2006-ZhuoCCV #hybrid
Extending the lifetime of fuel cell based hybrid systems (JZ, CC, NC, SBKV), pp. 562–567.
DAC-2005-BhardwajV #random
Leakage minimization of nano-scale circuits in the presence of systematic and random variations (SB, SBKV), pp. 541–546.
DAC-2005-RaoV #energy #set
Energy optimal speed control of devices with discrete speed sets (RR, SBKV), pp. 901–904.
DATE-2005-GhantaVPW #analysis #grid #power management #probability #process
Stochastic Power Grid Analysis Considering Process Variations (PG, SBKV, RP, JMW), pp. 964–969.
DAC-2004-AgarwalSBLNV #analysis #metric
Variational delay metrics for interconnect timing analysis (KA, DS, DB, FL, SRN, SBKV), pp. 381–384.
DAC-2004-ChopraV #algorithm #pseudo
Implicit pseudo boolean enumeration algorithms for input vector control (KC, SBKV), pp. 767–772.
DAC-2004-RajVW #process
A methodology to improve timing yield in the presence of process variations (SR, SBKV, JMW), pp. 448–453.
DATE-v2-2004-DasikaVCS #framework
A Framework for Battery-Aware Sensor Management (SD, SBKV, KC, RS), pp. 962–967.
DAC-2003-AgarwalBZV #bound #refinement #statistics
Computation and Refinement of Statistical Bounds on Circuit Delay (AA, DB, VZ, SBKV), pp. 348–353.
DATE-2003-AgarwalBZV #analysis #bound #statistics #using
Statistical Timing Analysis Using Bounds (AA, DB, VZ, SBKV), pp. 10062–10067.
DAC-2002-RakhmatovVC #scalability
Battery-conscious task sequencing for portable devices including voltage/clock scaling (DNR, SBKV, CC), pp. 189–194.
DAC-2002-VrudhulaBS #estimation
Estimation of the likelihood of capacitive coupling noise (SBKV, DB, SS), pp. 653–658.
DATE-1998-WangV #data-driven #optimisation
Data Driven Power Optimization of Sequential Circuits (QW, SBKV), pp. 686–691.
DAC-1997-WangVG #trade-off
An Investigation of Power Delay Trade-Offs on PowerPC Circuits (QW, SBKV, SG), pp. 425–428.
DAC-1993-LaiPV #composition #logic #synthesis
BDD Based Decomposition of Logic Functions with Application to FPGA Synthesis (YTL, MP, SBKV), pp. 642–647.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.