BibSLEIGH corpus
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Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
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Travelled to:
1 × Canada
1 × Germany
1 × United Kingdom
12 × USA
2 × Sweden
3 × France
Collaborated with:
F.Liu S.R.Nassif W.Wang M.Chen L.T.Clark K.Tan J.Velamala Y.Ye S.B.K.Vrudhula R.Vattikonda K.Sutaria S.Bhardwaj H.Zhang S.Ding P.McNeillie T.Syeda-Mahmood N.Mehta Z.Wei A.R.Newton R.Zheng J.B.Velamala T.Sato C.Chan J.Li R.LiVolsi M.Torres G.C.Das C.Y.Chan W.Zhao P.Ghanta S.Sinha G.Yeric V.Chandra B.Cline S.Baang S.Liu M.Li S.Hu A.Ramkumar R.Zhu R.Rajveev Y.Ma J.Suh C.Xu N.Hakim B.Bakkaloglu A.Khosla C.C.Lin H.Chiu J.Hu H.Lee Y.Wang X.Chen Y.Xie H.Yang R.Singhal A.Balijepalli A.R.Subramaniam S.Yang S.Chellappa J.Ni X.Yao N.D.Hindman E.Mintarno J.Skaf S.P.Boyd R.W.Dutton S.Mitra A.E.Caldwell A.B.Kahng F.Koushanfar H.Lu I.L.Markov M.Oliver D.Stroobandt D.Sylvester P.Chen D.Kadetotad Z.Xu A.Mohanty B.Lin J.Ye J.Seo S.Yu
Talks about:
model (8) circuit (7) optim (6) statist (4) analysi (4) design (4) under (4) age (4) technolog (3) variabl (3)

Person: Yu Cao


Contributed to:

DATE 20152015
ASE 20142014
DAC 20142014
ICPR 20142014
DAC 20122012
VLDB 20122012
DAC 20112011
DAC 20102010
DATE 20102010
KDD 20102010
DAC 20092009
DATE 20092009
DAC 20082008
ICPR 20082008
SIGMOD 20082008
DAC 20072007
DATE 20072007
DAC 20062006
DAC 20052005
ICPR v4 20042004
DAC 20002000

Wrote 26 papers:

DATE-2015-ChenKXMLYVSCY #algorithm #array #learning
Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip (PYC, DK, ZX, AM, BL, JY, SBKV, JsS, YC, SY), pp. 854–859.
ASE-2014-CaoZD #named
SymCrash: selective recording for reproducing crashes (YC, HZ, SD), pp. 791–802.
DAC-2014-SutariaRZRMC #modelling #random #simulation #validation
BTI-Induced Aging under Random Stress Waveforms: Modeling, Simulation and Silicon Validation (KS, AR, RZ, RR, YM, YC), p. 6.
ICPR-2014-CaoMS #image #segmentation
Segmentation of Anatomical Structures in Four-Chamber View Echocardiogram Images (YC, PM, TSM), pp. 568–573.
DAC-2012-SinhaYCCC #design #modelling #predict
Exploring sub-20nm FinFET design with predictive technology models (SS, GY, VC, BC, YC), pp. 283–288.
DAC-2012-VelamalaSSC #matter #physics #predict #statistics
Physics matters: statistical aging prediction under trapping/detrapping (JBV, KS, TS, YC), pp. 139–144.
VLDB-2012-CaoCLT #optimisation
Optimization of Analytic Window Functions (YC, CYC, JL, KLT), pp. 1244–1255.
DAC-2011-VelamalaLTC #design #logic
Design sensitivity of single event transients in scaled logic circuits (JV, RL, MT, YC), pp. 694–699.
DAC-2011-ZhengSXHBC #array #framework #platform #programmable
Programmable analog device array (PANDA): a platform for transistor-level analog reconfigurability (RZ, JS, CX, NH, BB, YC), pp. 322–327.
DAC-2010-ChellappaNYHVCCC #variability
In-situ characterization and extraction of SRAM variability (SC, JN, XY, NDH, JV, MC, YC, LTC), pp. 711–716.
DATE-2010-MintarnoSZVCBDM #self
Optimized self-tuning for circuit aging (EM, JS, RZ, JV, YC, SPB, RWD, SM), pp. 586–591.
DATE-2010-NassifMC #roadmap
A resilience roadmap (SRN, NM, YC), pp. 1011–1016.
KDD-2010-KhoslaCLCHL #approach #machine learning #predict
An integrated machine learning approach to stroke prediction (AK, YC, CCYL, HKC, JH, HL), pp. 183–192.
DAC-2009-YeLCC #analysis #layout #process #variability
Variability analysis under layout pattern-dependent rapid-thermal annealing process (YY, FL, MC, YC), pp. 551–556.
DATE-2009-0002CWCXY #optimisation
Gate replacement techniques for simultaneous leakage and aging optimization (YW, XC, WW, YC, YX, HY), pp. 328–333.
DAC-2008-YeLNC #modelling #simulation #statistics
Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness (YY, FL, SRN, YC), pp. 900–905.
ICPR-2008-CaoBLLH #classification #word
Audio-visual event classification via spatial-temporal-audio words (YC, SB, SHL, ML, SH), pp. 1–5.
SIGMOD-2008-CaoDCT #multi #optimisation #query
Optimizing complex queries with multiple relation instances (YC, GCD, CYC, KLT), pp. 525–538.
DAC-2007-SinghalBSLNC #analysis #modelling #simulation
Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation (RS, AB, ARS, FL, SRN, YC), pp. 823–828.
DAC-2007-WangYBVVLC #performance
The Impact of NBTI on the Performance of Combinational and Sequential Circuits (WW, SY, SB, RV, SBKV, FL, YC), pp. 364–369.
DATE-2007-ChenZLC #analysis #performance #statistics
Fast statistical circuit analysis with finite-point based transistor model (MC, WZ, FL, YC), pp. 1391–1396.
DAC-2006-BhardwajVGC #analysis #modelling #optimisation #process
Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits (SB, SBKV, PG, YC), pp. 791–796.
DAC-2006-VattikondaWC #design #modelling #robust
Modeling and minimization of PMOS NBTI effect for robust nanometer design (RV, WW, YC), pp. 1047–1052.
DAC-2005-CaoC #approach #modelling #performance #process #statistics #towards #variability
Mapping statistical process variations toward circuit performance variability: an analytical modeling approach (YC, LTC), pp. 658–663.
ICPR-v4-2004-WeiCN #image
Digital Image Restoration by Exposure-Splitting and Registration (ZW, YC, ARN), pp. 657–660.
DAC-2000-CaldwellCKKLMOSS #named
GTX: the MARCO GSRC technology extrapolation system (AEC, YC, ABK, FK, HL, ILM, MO, DS, DS), pp. 693–698.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.