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Travelled to:
1 × USA
Collaborated with:
J.Wenin J.Verhasselt M.V.Camp P.Guebels
Talks about:
constrain (1) parasit (1) system (1) layout (1) verif (1) vlsi (1) rule (1) base (1)

Person: Jean Leonard

DBLP DBLP: Leonard:Jean

Contributed to:

DAC 19891989

Wrote 1 papers:

DAC-1989-WeninVCLG #layout #rule-based #verification
Rule-based VLSI Verification System Constrained by Layout Parasitics (JW, JV, MVC, JL, PG), pp. 662–667.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.