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Travelled to:
1 × France
Collaborated with:
C.K.Lo M.Wu R.Tsay
Talks about:
accur (2) processor (1) system (1) simul (1) model (1) level (1) count (1) fast (1) cycl (1)

Person: Li-Chun Chen

DBLP DBLP: Chen:Li=Chun

Contributed to:

DATE 20112011

Wrote 1 papers:

DATE-2011-LoCWT #modelling #performance #simulation
Cycle-count-accurate processor modeling for fast and accurate system-level simulation (CKL, LCC, MHW, RST), pp. 341–346.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.