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Travelled to:
2 × France
2 × Germany
5 × USA
Collaborated with:
M.Wu E.S.Kuh P.Wang C.Fu J.Koehl Y.Huang H.Wu S.Chen C.Chen M.Shih C.Hsu Y.Lu C.K.Lo L.Chen W.Lee C.Chuang F.Yu B.Zeng C.Lee
Talks about:
simul (8) approach (4) system (4) effici (4) multi (4) synchron (3) model (3) core (3) determinist (2) placement (2)

Person: Ren-Song Tsay

DBLP DBLP: Tsay:Ren=Song

Contributed to:

DATE 20142014
DATE 20132013
DAC 20122012
DAC 20112011
DATE 20112011
DATE 20102010
DAC 19921992
DAC 19911991
DAC 19881988

Wrote 11 papers:

DATE-2014-ChenCT #performance #simulation
An activity-sensitive contention delay model for highly efficient deterministic full-system simulations (SYC, CHC, RST), pp. 1–6.
DATE-2013-YuZHWLT #approach #manycore #set #simulation
A critical-section-level timing synchronization approach for deterministic multi-core instruction set simulations (FWY, BHZ, YHH, HIW, CRL, RST), pp. 643–648.
DAC-2012-HuangLWT #interface
A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulation (YHH, YSL, HIW, RST), pp. 127–132.
DAC-2011-WuWFT #distributed #manycore #scheduling #simulation
A high-parallelism distributed scheduling mechanism for multi-core instruction-set simulation (MHW, PCW, CYF, RST), pp. 339–344.
DATE-2011-FuWT #approach #manycore #performance #simulation
A shared-variable-based synchronization approach to efficient cache coherence simulation for multi-core systems (CYF, MHW, RST), pp. 347–352.
DATE-2011-LoCWT #modelling #performance #simulation
Cycle-count-accurate processor modeling for fast and accurate system-level simulation (CKL, LCC, MHW, RST), pp. 341–346.
DATE-2011-WangWT #approach #modelling #named #performance #scheduling #simulation
DOM: A Data-dependency-Oriented Modeling approach for efficient simulation of OS preemptive scheduling (PCW, MHW, RST), pp. 335–340.
DATE-2010-WuLCT #abstraction #automation #generative #multi #performance
Automatic generation of software TLM in multiple abstraction layers for efficient HW/SW co-simulation (MHW, WCL, CYC, RST), pp. 1177–1182.
DAC-1992-ShihKT #clustering #multi
Performance-Driven System Partitioning on Multi-Chip Modules (MS, ESK, RST), pp. 53–56.
DAC-1991-TsayK #approach #optimisation #performance
An Analytic Net Weighting Approach for Performance Optimization in Circuit Placement (RST, JK), pp. 620–625.
DAC-1988-TsayKH #algorithm #named #performance
Proud: A Fast Sea-of-Gates Placement Algorithm (RST, ESK, CPH), pp. 318–323.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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