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Collaborated with:
U.Mathur D.Kini P.Madhusudan P.S.Duggirala C.Fan S.Mitra R.Chadha A.P.Sistla B.Qi M.S.Bauer S.Saha Adithya Murali Paul Krogmeier
Talks about:
linear (4) race (4) verif (3) dynam (3) decid (3) synthesi (2) program (2) predict (2) system (2) happen (2)

Person: Mahesh Viswanathan 0001

DBLP DBLP: 0001:Mahesh_Viswanathan

Contributed to:

ESEC/FSE 20182018
CAV (1) 20162016
CAV (1) 20172017
CAV (1) 20182018
CAV (2) 20182018
CSL 20182018
OOPSLA 20182018
PLDI 20172017
POPL 20192019
POPL 20202020
ASPLOS 20202020

Wrote 13 papers:

ESEC-FSE-2018-KiniM0 #concurrent #detection
Data race detection on compressed traces (DK, UM, MV0), pp. 26–37.
CAV-2016-Duggirala0 #linear #simulation #verification
Parsimonious, Simulation Based Verification of Linear Systems (PSD, MV0), pp. 477–494.
CAV-2016-FanQM0D #analysis #automation #hybrid #modelling #reachability
Automatic Reachability Analysis for Nonlinear Hybrid Models with C2E2 (CF, BQ, SM, MV0, PSD), pp. 531–538.
CAV-2017-FanQM0 #composition #data-driven #named #reasoning #verification
DryVR: Data-Driven Verification and Compositional Reasoning for Automotive Systems (CF, BQ, SM, MV0), pp. 441–461.
CAV-2018-FanMM0 #linear #specification #synthesis
Controller Synthesis Made Real: Reach-Avoid Specifications and Linear Dynamics (CF, UM, SM, MV0), pp. 347–366.
CAV-2018-BauerCS0 #model checking #protocol #random #security
Model Checking Indistinguishability of Randomized Security Protocols (MSB, RC, APS, MV0), pp. 117–135.
CSL-2018-ChadhaS0 #approximate #automaton #probability #regular expression
Approximating Probabilistic Automata by Regular Languages (RC, APS, MV0), p. 23.
CSL-2018-MadhusudanMS0 #decidability #higher-order #logic #synthesis
A Decidable Fragment of Second Order Logic With Applications to Synthesis (PM, UM, SS, MV0), p. 19.
OOPSLA-2018-MathurK0 #concurrent #detection #power of #predict #what
What happens-after the first race? enhancing the predictive power of happens-before based dynamic race detection (UM, DK, MV0), p. 29.
PLDI-2017-KiniM0 #linear #predict
Dynamic race prediction in linear time (DK, UM, MV0), pp. 157–170.
POPL-2019-MathurMV #decidability #source code #verification
Decidable verification of uninterpreted programs (UM, PM, MV0), p. 29.
POPL-2020-MathurMKMV #memory management #safety #source code
Deciding memory safety for single-pass heap-manipulating programs (UM, AM, PK, PM, MV0), p. 29.
ASPLOS-2020-Mathur0 #linear #using
Atomicity Checking in Linear Time using Vector Clocks (UM, MV0), pp. 183–199.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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