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XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
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Travelled to:
1 × Belgium
1 × Estonia
1 × Israel
1 × Portugal
1 × Spain
1 × Turkey
1 × USA
Collaborated with:
E.M.Clarke P.F.Mihancea S.V.A.Campos D.Peled B.Genest A.Muscholl W.R.Marrero S.Sapra S.Chaki A.Gurfinkel R.P.Kurshan V.Levin H.Yenigün M.Büchler K.Hossen R.Groz C.Oriat A.Armando W.Arsac T.Avanesov M.Barletta A.Calvi A.Cappai R.Carbone Y.Chevalier L.Compagna J.Cuéllar G.Erzse S.Frau S.Mödersheim D.v.Oheimb G.Pellegrino S.E.Ponta M.Rocchetto M.Rusinowitch M.T.Dashti M.Turuani L.Viganò
Talks about:
secur (3) properti (2) quantit (2) partial (2) verifi (2) system (2) verus (2) order (2) model (2) tool (2)

Person: Marius Minea

DBLP DBLP: Minea:Marius

Contributed to:

CSMR-WCRE 20142014
ICTSS 20132013
TACAS 20122012
FoSSaCS 20042004
TACAS 19981998
CAV 19971997
LCT-RTS 19951995

Wrote 8 papers:

CSMR-WCRE-2014-BuchlerHMMGO #model inference #security #testing
Model inference and security testing in the spacios project (MB, KH, PFM, MM, RG, CO), pp. 411–414.
CSMR-WCRE-2014-MihanceaM #named #security #verification #web
JMODEX: Model extraction for verifying security properties of web applications (PFM, MM), pp. 450–453.
ICTSS-2013-SapraMCGC #execution #fault #python #source code #symbolic computation #using
Finding Errors in Python Programs Using Dynamic Symbolic Execution (SS, MM, SC, AG, EMC), pp. 283–289.
TACAS-2012-ArmandoAABCCCCCCEFMMOPPRRDTV #architecture #automation #framework #platform #security #trust #validation
The AVANTSSAR Platform for the Automated Validation of Trust and Security of Service-Oriented Architectures (AA, WA, TA, MB, AC, AC, RC, YC, LC, JC, GE, SF, MM, SM, DvO, GP, SEP, MR, MR, MTD, MT, LV), pp. 267–282.
FoSSaCS-2004-GenestMMP #partial order #specification #using #verification
Specifying and Verifying Partial Order Properties Using Template MSCs (BG, MM, AM, DP), pp. 195–210.
TACAS-1998-KurshanLMPY #partial order #reduction
Static Partial Order Reduction (RPK, VL, MM, DP, HY), pp. 345–357.
CAV-1997-CamposCM #approach #realtime #verification
The Verus Tool: A Quantitative Approach to the Formal Verification of Real-Time Systems (SVAC, EMC, MM), pp. 452–455.
LCT-RTS-1995-CamposCMM #analysis #finite #named #realtime
Verus: A Tool for Quantitative Analysis of Finite-State Real-Time Systems (SVAC, EMC, WRM, MM), pp. 70–78.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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